Patents by Inventor Gwan Sin Chang
Gwan Sin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140101623Abstract: A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i?j. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.Type: ApplicationFiled: December 12, 2013Publication date: April 10, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pi-Tsung CHEN, Ming-Hui CHIH, Ken-Hsien HSIEH, Wei-Long WANG, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU, Wen-Ju YANG, Gwan Sin CHANG, Yung-Sung YEN
-
Patent number: 8633516Abstract: The present disclosure provides a semiconductor device. The device includes a substrate, a fin structure formed by a first semiconductor material, a gate region on a portion of the fin, a source region and a drain region separated by the gate region on the substrate and a source/drain stack on the source and drain region. A low portion of the source/drain stack is formed by a second semiconductor material and it contacts a low portion of the fin in the gate region. An upper portion of the source/drain stack is formed by a third semiconductor material and it contacts an upper portion of the fin in the gate region.Type: GrantFiled: September 28, 2012Date of Patent: January 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Gwan Sin Chang, Kuo-Cheng Ching, Chun Chung Su, Shi Ning Ju
-
Patent number: 8631379Abstract: Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.Type: GrantFiled: February 9, 2010Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pi-Tsung Chen, Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Wen-Ju Yang, Gwan Sin Chang, Yung-Sung Yen
-
Patent number: 8572537Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.Type: GrantFiled: June 19, 2012Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan-Sin Chang, Chien-Wen Chen
-
Patent number: 8336002Abstract: An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.Type: GrantFiled: March 20, 2007Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gwan Sin Chang, Yi-Kan Cheng, Ivy Chiu, Ke-Ying Su
-
Publication number: 20120260225Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.Type: ApplicationFiled: June 19, 2012Publication date: October 11, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen
-
Patent number: 8286114Abstract: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.Type: GrantFiled: August 2, 2007Date of Patent: October 9, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Mong Song Liang, Sheng-Chen Chung, Chih-Tsung Yao, Jung-Hui Kao, Chung Long Cheng, Gary Shen, Gwan Sin Chang
-
Patent number: 8239806Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.Type: GrantFiled: December 30, 2009Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Gwan Sin Chang, Wen-Ju Yang, Zhe-Wei Jiang, Yi-Kan Cheng, Lee-Chung Lu
-
Patent number: 8227869Abstract: Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.Type: GrantFiled: October 28, 2011Date of Patent: July 24, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Chung-Te Lin, Yen-Sen Wang, Yao-Jen Chuang, Gwan Sin Chang
-
Patent number: 8214784Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.Type: GrantFiled: September 29, 2010Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen
-
Patent number: 8136168Abstract: An encryption and decryption interface for integrated circuit (IC) design with design-for-manufacturing (DFM). The interface includes a decryption module embedded in an IC design tool; an encrypted DFM data provided to an IC designer authorized for utilizing the encrypted DFM data; and a private key provided to the IC designer for decrypting the encrypted DFM data in the IC design tool.Type: GrantFiled: March 16, 2007Date of Patent: March 13, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Kan Cheng, Gwan Sin Chang, Jill Liu, Hsiao-Shu Chiao
-
Publication number: 20120043618Abstract: Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.Type: ApplicationFiled: October 28, 2011Publication date: February 23, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Chung-Te Lin, Yen-Sen Wang, Yao-Jen Chuang, Gwan Sin Chang
-
Patent number: 8122394Abstract: A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.Type: GrantFiled: September 17, 2008Date of Patent: February 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Chung-Te Lin, Yen-Sen Wang, Yao-Jen Chuang, Gwan Sin Chang
-
Patent number: 8051392Abstract: A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.Type: GrantFiled: September 17, 2008Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Chung-Te Lin, Yen-Sen Wang, Yao-Jen Chuang, Gwan Sin Chang
-
Publication number: 20110197168Abstract: Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.Type: ApplicationFiled: February 9, 2010Publication date: August 11, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pi-Tsung Chen, Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Wen-Ju Yang, Gwan Sin Chang, Yung-Sung Yen
-
Publication number: 20110193234Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.Type: ApplicationFiled: February 9, 2010Publication date: August 11, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng, Li-Chun Tien, Lee-Chung Lu
-
Patent number: 7966596Abstract: This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof.Type: GrantFiled: August 27, 2008Date of Patent: June 21, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lee-Chung Lu, Chung-Hsing Wang, Ping Chung Li, Chun-Hui Tai, Li-Chun Tien, Gwan Sin Chang
-
Publication number: 20110119648Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.Type: ApplicationFiled: December 30, 2009Publication date: May 19, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huang-Yu Chen, Yuan-Te Hou, Gwan Sin Chang, Wen-Ju Yang, Zhe-Wei Jiang, Yi-Kan Cheng, Lee-Chung Lu
-
Patent number: 7904844Abstract: An automated system for checking an integrated circuit cell layout includes searching the cell layout for a sub-area containing a predefined identifier, determining a reference cell layout corresponding to the predefined identifier, verifying the cell layout by comparing the cell layout to the reference cell layout to determine if a cell is of concern, and reporting the cell of concern to a user.Type: GrantFiled: December 3, 2007Date of Patent: March 8, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gwan Sin Chang, Cheng-Hung Yeh, Feng-Ming Chang, Ping-Wei Wang
-
Publication number: 20110023003Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.Type: ApplicationFiled: September 29, 2010Publication date: January 27, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen