Abstract: A memory card is structured to support a variety of applications by dividing a storage region into a plurality of sub storage regions, each sub storage region being assigned a particular data format associated with each of a plurality of application programs stored in a controller of the memory card. The data stored in each of the sub storage regions co-exists compatibly in the memory card. This allows for a multiplicity of applications, which can be made available through the use of a single memory card.

Abstract: A memory module having a high data processing rate and high capacity is provided. The memory module may include a memory chip, a controller controlling an operation of the memory chip, an optical detector converting an external input signal into an internal input signal to transmit the converted signal to the controller, and an optical generator converting an internal output signal received from the controller into an external output signal. The optical detector converts an external input optical signal into an internal input signal to transmit the converted signal to the controller. The optical generator converts an internal output signal received from the controller into an external output optical signal.

Abstract: A module substrate structure may include a substrate, a passive device mounted on the substrate, and a protection layer covering the passive device. The protection layer may cover the passive device either completely or partly. Where a plurality of passive devices are present, the protection layer may cover either all or a selected number of the passive devices. A semiconductor module may include the module substrate structure in addition to a semiconductor chip mounted on the substrate, and an encapsulant covering the substrate. The semiconductor chip may be electrically connected to the passive device. Manufacturing processes (e.g., plasma treatment) may cause the passive device to be bombarded by ions and become electrically charged. Consequently, the electrical charges built up in the passive device may discharge (flow) and cause damage to the semiconductor chip.

Abstract: A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may be provided on the upper surface of the circuit substrate. An IC chip may be provided on the lower surface of the circuit substrate. The IC chip may have an active surface with wire lands and bump lands. Chip bumps may be provided on the bump land. The wire bonding pads of the circuit substrate may be connected to the wire lands of the IC chip using bonding wires. The chip bumps of the upper unit package may be connected to the chip bonding pads of the lower unit package. An IC chip may include a substrate. A conductive layer may be provided on the substrate. The conductive layer may define a bump land for supporting a chip bump and a wire land for connecting to a bonding wire.

Abstract: A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may be provided on the upper surface of the circuit substrate. An IC chip may be provided on the lower surface of the circuit substrate. The IC chip may have an active surface with wire lands and bump lands. Chip bumps may be provided on the bump land. The wire bonding pads of the circuit substrate may be connected to the wire lands of the IC chip using bonding wires. The chip bumps of the upper unit package may be connected to the chip bonding pads of the lower unit package. An IC chip may include a substrate. A conductive layer may be provided on the substrate. The conductive layer may define a bump land for supporting a chip bump and a wire land for connecting to a bonding wire.

Abstract: A memory card is disclosed and includes an adaptor comprising a card controller controlling operations of the memory card, and a memory package capable of being electrically/mechanically connected to and separated from the adaptor via a connection structure. A method of using a memory card is also disclosed and includes connecting the adaptor to the memory package via the connection structure, identifying a memory card type in relation to the functional nature of the card controller upon connection of the memory package with the adaptor, and communicating data between the card controller and memory package.

Abstract: A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may be provided on the upper surface of the circuit substrate. An IC chip may be provided on the lower surface of the circuit substrate. The IC chip may have an active surface with wire lands and bump lands. Chip bumps may be provided on the bump land. The wire bonding pads of the circuit substrate may be connected to the wire lands of the IC chip using bonding wires. The chip bumps of the upper unit package may be connected to the chip bonding pads of the lower unit package. An IC chip may include a substrate. A conductive layer may be provided on the substrate. The conductive layer may define a bump land for supporting a chip bump and a wire land for connecting to a bonding wire.

Abstract: A POP (package-on-package) structure includes a first and a second semiconductor chip and a connecting structure. The first semiconductor chip is disposed on a first substrate that includes a plurality of first internal terminals and a plurality of first external terminals. The second semiconductor chip is disposed on a second substrate that includes a plurality of second internal terminals and a plurality of second external terminals. The connecting structure electrically connects at least one of the first external terminals to at least one of the second external terminals.

Abstract: A semiconductor chip package mounting structure may mount a semiconductor chip package on a module board by implementing a flexible circuit board. The semiconductor chip package may be electrically connected to a first surface of the flexible circuit board and the module board may be electrically connected to a second surface of the flexible circuit board.

Abstract: An interposer may include a base substrate supporting an array of conductive lands. The conductive land may have an identical shape and size. The conductive lands may be provided at regular intervals on the base substrate. The conductive land pitch may be determined such that adjacent conductive lands may be electrically connected by one end of an electric connection member. Alternatively, each conductive land may provide respective bonding locations to which ends of two different electric connection members may be bonded. A stacked chip package may include an interposer that may be fabricated by cutting an interposer to size. In the stacked chip package, electrical connections may be made through the interposer between an upper semiconductor chip and a package substrate, between the upper semiconductor chip and a lower semiconductor chip, and/or between the lower semiconductor chip and the package substrate.

Abstract: A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may be provided on the upper surface of the circuit substrate. An IC chip may be provided on the lower surface of the circuit substrate. The IC chip may have an active surface with wire lands and bump lands. Chip bumps may be provided on the bump land. The wire bonding pads of the circuit substrate may be connected to the wire lands of the IC chip using bonding wires. The chip bumps of the upper unit package may be connected to the chip bonding pads of the lower unit package. An IC chip may include a substrate. A conductive layer may be provided on the substrate. The conductive layer may define a bump land for supporting a chip bump and a wire land for connecting to a bonding wire.