Patents by Inventor Gweltaz Gaudin

Gweltaz Gaudin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240392476
    Abstract: A method of fabricating a composite structure including a thin layer of single-crystal silicon carbide on a polycrystalline SiC carrier substrate includes: forming a polycrystalline SiC layer on a donor substrate, at least a surface portion of which is made of single-crystal SiC; before or after forming the polycrystalline SiC layer, implanting ionic species into the surface portion of the donor substrate, so as to form a plane of weakness delimiting a thin single-crystal SiC layer to be transferred; after the implanting of the ionic species and the forming of the polycrystalline SiC layer, bonding the donor substrate and the polycrystalline SiC carrier substrate, the polycrystalline SiC layer being at the bonding interface; and detaching the donor substrate along the plane of weakness, so as to transfer the polycrystalline SiC layer and the thin single-crystal SiC layer onto the polycrystalline SiC carrier substrate.
    Type: Application
    Filed: October 3, 2022
    Publication date: November 28, 2024
    Inventors: Ionut Radu, Hugo Biard, Gweltaz Gaudin
  • Publication number: 20240395603
    Abstract: A method for manufacturing a composite structure having a layer of monocrystalline silicon carbide on a polycrystalline silicon carbide carrier substrate includes: providing an initial substrate of polycrystalline silicon carbide, having a front face and comprising grains, the average size of which is greater than 0.5 ?m; forming a polycrystalline silicon carbide surface layer on the initial substrate to form the carrier substrate, the surface layer including grains having an average size of less than 500 nm and having a thickness of between 50 nm and 50 ?m; preparing a free surface of the surface layer of the carrier substrate to obtain a roughness of less than 1 nm RMS; (d) a step of transferring the useful layer onto the carrier substrate, by applying molecular bonding, the surface layer located between the useful layer and the initial substrate. A carrier substrate and a composite structure are formed by the method.
    Type: Application
    Filed: September 20, 2022
    Publication date: November 28, 2024
    Inventors: Gweltaz Gaudin, Christophe Maleville, Sidoine Odoul, Ionut Radu, Hugo Biard
  • Publication number: 20240312831
    Abstract: A method for producing a semiconductor structure comprises: a) provision of a monocrystalline silicon carbide donor substrate and a silicon carbide support substrate; b) production of a useful layer to be transferred, comprising—implanting light species in the donor substrate at a front face, so as to form a damage profile, the profile having a main peak of deep-level defects defining a buried brittle plane and a secondary peak of defects defining a damaged surface layer, and—removing the damaged surface layer by chemical etching and/or chemical mechanical polishing of the front face of the donor substrate, so as to form a new front surface of the donor substrate; c) assembly of donor substrate with the support substrate; and d) separation along the buried fragile plane, leading to the transfer of the useful layer onto the support substrate, so as to form the semiconductor structure.
    Type: Application
    Filed: May 25, 2022
    Publication date: September 19, 2024
    Inventors: Alexis Drouin, Gweltaz Gaudin, Séverin Rouchier, Walter Schwarzenbach, Julie Widiez, Emmanuel Rolland
  • Patent number: 12087631
    Abstract: A method for producing a composite structure comprises providing a donor substrate including a single-crystal material, and a support substrate having a first alignment pattern on a face or edge of the support substrate. A heat treatment is applied at least to the donor substrate to bring about a surface reorganization on at least one face of the donor substrate. The surface reorganization results in formation of first steps of nanometric amplitude, which are parallel to a first main axis. The donor substrate and the support substrate are optically aligned, to better than ±0.1° between a locating mark indicating the first main axis on the donor substrate and at least one alignment pattern of the support substrate. The donor substrate and the support substrate are then assembled together, and a thin layer is transferred from the donor substrate onto the support substrate.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: September 10, 2024
    Assignee: SOITEC
    Inventor: Gweltaz Gaudin
  • Publication number: 20240266172
    Abstract: The invention relates to a semiconductor structure (100) that comprises a useful layer (10) made of monocrystalline semiconductor material and extending along a main plane (x, y), a support substrate (30) made of semiconductor material, and an interface area (20) between the useful layer (10) and the support substrate (30), the support substrate extending parallel to the main plane (x, y), the structure (100) being characterised in that the interface area (20) comprises nodules (21) that:—are electrically conductive, in that they contain a metal material forming ohmic contact with the useful layer (10) and the support substrate (30);—have a thickness, along an axis (z) normal to the main plane (x, y) , of less than or equal to 30 nm;—are separate or adjoining, the separate nodules (21) being separated from each other by regions (22) of direct contact between the useful layer (10) and the support substrate (30). The invention also relates to a method for manufacturing the structure (100).
    Type: Application
    Filed: June 8, 2021
    Publication date: August 8, 2024
    Inventors: Frédéric Allibert, Didier Landru, Oleg Kononchuk, Eric Guiot, Gweltaz Gaudin, Julie Widiez, Franck Fournel
  • Publication number: 20240170284
    Abstract: A method for producing a semiconductor structure, comprises: a) providing a temporary substrate made of graphite having a grain size of between 4 microns and 35 microns, a porosity of between 6 and 17%, and a coefficient of thermal expansion of between 4×10-6/° C. and 5×10-6/° C.; b) depositing, on a front face of the temporary substrate, a carrier layer made of polycrystalline silicon carbide having a thickness of between 10 microns and 200 microns, c) transferring a working layer made of monocrystalline silicon carbide to the carrier layer to form a composite structure, the transfer implementing bonding by molecular adhesion, d) forming an active layer on the working layer, e) and removing the temporary substrate to form the semiconductor structure, the structure including the active layer, the working layer and the carrier layer. A composite structure is obtained in an intermediate step of the production method.
    Type: Application
    Filed: March 3, 2022
    Publication date: May 23, 2024
    Inventors: Gweltaz Gaudin, Christophe Maleville, lonut Radu, Hugo Biard
  • Publication number: 20240145294
    Abstract: A method for manufacturing a semiconductor structure comprises: a) providing a temporary substrate comprising a material having a coefficient of thermal expansion close to that of silicon carbide; b) forming an intermediate graphite layer on a front face of the temporary substrate; c) depositing, on the intermediate layer, a polycrystalline silicon carbide support layer having a thickness of between 10 microns and 200 microns, d) transferring a useful monocrystalline silicon carbide layer onto the support layer in order to form a composite structure, the transfer using molecular adhesion bonding, e) forming an active layer on the useful layer, and f) disassembling, at an interface of or inside the intermediate layer, to structure to form the semiconductor structure including the active layer, the useful layer and the support layer. A composite structure is obtained by the method.
    Type: Application
    Filed: March 3, 2022
    Publication date: May 2, 2024
    Inventors: Hugo Biard, Gweltaz Gaudin
  • Publication number: 20240030033
    Abstract: A method for producing a semiconductor structure comprises: a) providing a working layer of a semiconductor material; b) providing a carrier substrate of a semiconductor material; c) depositing a thin film of a semiconductor material different from that or those of the working layer and the carrier substrate on a free face to be joined of the working layer and/or the carrier substrate; d) directly joining the free faces of the working layer and the carrier substrate, e) annealing the joined structure at an elevated temperature to bring about segmentation of the encapsulated thin film and form a semiconductor structure comprising an interface region between the working layer and the carrier substrate, the interface region comprising: —regions of direct contact between the working layer and the carrier substrate; and —agglomerates comprising the semiconductor material of the thin film adjacent the regions of direct contact.
    Type: Application
    Filed: November 29, 2021
    Publication date: January 25, 2024
    Inventors: Gweltaz Gaudin, Ionut Radu, Franck Fournel, Julie Widiez, Didier Landru
  • Publication number: 20240030061
    Abstract: A donor substrate for transferring a single-crystal thin layer made of a first material, onto a receiver substrate. The donor substrate comprises: —a buried weakened plane delimiting an upper portion and a lower portion of the donor substrate, —in the upper portion, a first layer, a second layer adjacent to the buried weakened plane, and a stop layer between the first layer and the second layer the first layer composed of the first material, the stop layer being formed of a second material, —an amorphized sub-portion, made amorphous by ion implantation, having a thickness less than that of the upper portion, and including at least the first layer; the second layer comprising at least one single-crystal sub-layer, adjacent to the buried weakened plane. Two embodiments of a method may be used for transferring a single-crystal thin layer from the donor substrate.
    Type: Application
    Filed: November 19, 2021
    Publication date: January 25, 2024
    Inventors: Larry Vincent, Shay Reboh, Lucie Le Van-Jodin, Frédéric Milesi, Ludovic Ecarnot, Gweltaz Gaudin, Didier Landru
  • Publication number: 20230230868
    Abstract: A temporary substrate, which is detachable at a detachment temperature higher than 1000° C. comprises: a semiconductor working layer extending along a main plane, a carrier substrate, an intermediate layer having a thickness less than 20 nm arranged between the working layer and the carrier substrate, a bonding interface located in or adjacent the intermediate layer, gaseous atomic species distributed according to a concentration profile along the axis normal to the main plane, the atoms remaining trapped in the intermediate layer and/or in an adjacent layer of the carrier substrate with a thickness less than or equal to 10 nm and/or in an adjacent sublayer of the working layer with a thickness less than or equal to 10 nm when the temporary substrate is subjected to a temperature lower than the detachment temperature.
    Type: Application
    Filed: April 26, 2021
    Publication date: July 20, 2023
    Inventors: Hugo Biard, Gweltaz Gaudin, Séverin Rouchier, Didier Landru
  • Publication number: 20230129131
    Abstract: A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 27, 2023
    Inventors: Bich-Yen Nguyen, Gweltaz Gaudin
  • Publication number: 20230040826
    Abstract: The disclosure relates to a method of joining two semi-conductor substrates by molecular adhesion comprising: a step a) of bringing a first and a second substrate into intimate contact in order to form an assembly having a bonding interface; a step b) of reaction-annealing the bonding interface at a first temperature higher than a predetermined first temperature, this step b) generating bubbles at the joining interface; a step c) of at least partially debonding the two substrates at the bonding interface in order to eliminate the bubbles; and a step d) of bringing the first and the second substrate into intimate contact at the bonding interface in order to reform the assembly.
    Type: Application
    Filed: December 15, 2020
    Publication date: February 9, 2023
    Inventors: Gweltaz Gaudin, Céline Futin
  • Publication number: 20220359293
    Abstract: The invention relates to a process for manufacturing a composite structure comprising a thin layer made of a first single-crystal material positioned on a support substrate.
    Type: Application
    Filed: December 15, 2020
    Publication date: November 10, 2022
    Inventor: Gweltaz Gaudin
  • Publication number: 20220298007
    Abstract: A method for sealing cavities using membranes, the method including a) forming cavities arranged in a matrix, of a depth p, a characteristic dimension a, and spaced apart by a spacing b; and b) forming membranes, sealing the cavities, by transferring a sealing film. The method further includes a step a1), executed before step b), of forming a first contour on the front face and/or on the sealing face, the first contour comprising a first trench having a width L and a first depth p1, the formation of the first contour being executed such that after step b) the cavities are circumscribed by the first contour, said first contour being at a distance G from the cavities between one-fifth of b and five b.
    Type: Application
    Filed: August 18, 2020
    Publication date: September 22, 2022
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Thierry SALVETAT, Bruno GHYSELEN, Lamine BENAISSA, Caroline COUTIER, Gweltaz GAUDIN
  • Patent number: 11239108
    Abstract: A process for producing a donor substrate for creating a three-dimensional integrated structure comprises the following steps: providing a semiconductor substrate comprising a surface layer, referred to as an active layer, and a layer comprising a plurality of cavities extending beneath the active layer, each cavity being separated from an adjacent cavity by a partition, forming an electronic device in a region of the active layer located plumb with a cavity, depositing a protective mask on the active layer so as to cover the electronic device while at the same time exposing a region of the active layer located plumb with each partition, and implanting atomic species through regions of the active layer exposed by the mask to form a weakened zone in each partition.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 1, 2022
    Assignee: Soitec
    Inventors: Gweltaz Gaudin, Didier Landru, Bruno Ghyselen
  • Patent number: 11156778
    Abstract: A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: October 26, 2021
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Gweltaz Gaudin
  • Patent number: 11159140
    Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a free first surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer. The hybrid structure further comprises a trapping layer disposed between the useful layer and the support substrate, and at least one functional interface of predetermined roughness between the useful layer and the trapping layer.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 26, 2021
    Assignee: Soitec
    Inventors: Gweltaz Gaudin, Isabelle Huyet
  • Publication number: 20210057268
    Abstract: A process for producing a donor substrate for creating a three-dimensional integrated structure comprises the following steps: providing a semiconductor substrate comprising a surface layer, referred to as an active layer, and a layer comprising a plurality of cavities extending beneath the active layer, each cavity being separated from an adjacent cavity by a partition, forming an electronic device in a region of the active layer located plumb with a cavity, depositing a protective mask on the active layer so as to cover the electronic device while at the same time exposing a region of the active layer located plumb with each partition, and implanting atomic species through regions of the active layer exposed by the mask to form a weakened zone in each partition.
    Type: Application
    Filed: March 22, 2019
    Publication date: February 25, 2021
    Inventors: Gweltaz Gaudin, Didier Landru, Bruno Ghyselen
  • Publication number: 20200336127
    Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a free first surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer. The hybrid structure further comprises a trapping layer disposed between the useful layer and the support substrate, and at least one functional interface of predetermined roughness between the useful layer and the trapping layer.
    Type: Application
    Filed: July 7, 2020
    Publication date: October 22, 2020
    Inventors: Gweltaz Gaudin, Isabelle Huyet
  • Publication number: 20190372552
    Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a free first surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer. The hybrid structure further comprises a trapping layer disposed between the useful layer and the support substrate, and at least one functional interface of predetermined roughness between the useful layer and the trapping layer.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 5, 2019
    Inventors: Gweltaz Gaudin, Isabelle Huyet