Patents by Inventor Gweltaz Gaudin

Gweltaz Gaudin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220359293
    Abstract: The invention relates to a process for manufacturing a composite structure comprising a thin layer made of a first single-crystal material positioned on a support substrate.
    Type: Application
    Filed: December 15, 2020
    Publication date: November 10, 2022
    Inventor: Gweltaz Gaudin
  • Publication number: 20220298007
    Abstract: A method for sealing cavities using membranes, the method including a) forming cavities arranged in a matrix, of a depth p, a characteristic dimension a, and spaced apart by a spacing b; and b) forming membranes, sealing the cavities, by transferring a sealing film. The method further includes a step a1), executed before step b), of forming a first contour on the front face and/or on the sealing face, the first contour comprising a first trench having a width L and a first depth p1, the formation of the first contour being executed such that after step b) the cavities are circumscribed by the first contour, said first contour being at a distance G from the cavities between one-fifth of b and five b.
    Type: Application
    Filed: August 18, 2020
    Publication date: September 22, 2022
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Thierry SALVETAT, Bruno GHYSELEN, Lamine BENAISSA, Caroline COUTIER, Gweltaz GAUDIN
  • Patent number: 11239108
    Abstract: A process for producing a donor substrate for creating a three-dimensional integrated structure comprises the following steps: providing a semiconductor substrate comprising a surface layer, referred to as an active layer, and a layer comprising a plurality of cavities extending beneath the active layer, each cavity being separated from an adjacent cavity by a partition, forming an electronic device in a region of the active layer located plumb with a cavity, depositing a protective mask on the active layer so as to cover the electronic device while at the same time exposing a region of the active layer located plumb with each partition, and implanting atomic species through regions of the active layer exposed by the mask to form a weakened zone in each partition.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 1, 2022
    Assignee: Soitec
    Inventors: Gweltaz Gaudin, Didier Landru, Bruno Ghyselen
  • Patent number: 11159140
    Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a free first surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer. The hybrid structure further comprises a trapping layer disposed between the useful layer and the support substrate, and at least one functional interface of predetermined roughness between the useful layer and the trapping layer.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 26, 2021
    Assignee: Soitec
    Inventors: Gweltaz Gaudin, Isabelle Huyet
  • Patent number: 11156778
    Abstract: A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: October 26, 2021
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Gweltaz Gaudin
  • Publication number: 20210057268
    Abstract: A process for producing a donor substrate for creating a three-dimensional integrated structure comprises the following steps: providing a semiconductor substrate comprising a surface layer, referred to as an active layer, and a layer comprising a plurality of cavities extending beneath the active layer, each cavity being separated from an adjacent cavity by a partition, forming an electronic device in a region of the active layer located plumb with a cavity, depositing a protective mask on the active layer so as to cover the electronic device while at the same time exposing a region of the active layer located plumb with each partition, and implanting atomic species through regions of the active layer exposed by the mask to form a weakened zone in each partition.
    Type: Application
    Filed: March 22, 2019
    Publication date: February 25, 2021
    Inventors: Gweltaz Gaudin, Didier Landru, Bruno Ghyselen
  • Publication number: 20200336127
    Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a free first surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer. The hybrid structure further comprises a trapping layer disposed between the useful layer and the support substrate, and at least one functional interface of predetermined roughness between the useful layer and the trapping layer.
    Type: Application
    Filed: July 7, 2020
    Publication date: October 22, 2020
    Inventors: Gweltaz Gaudin, Isabelle Huyet
  • Publication number: 20190372552
    Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a free first surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer. The hybrid structure further comprises a trapping layer disposed between the useful layer and the support substrate, and at least one functional interface of predetermined roughness between the useful layer and the trapping layer.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 5, 2019
    Inventors: Gweltaz Gaudin, Isabelle Huyet
  • Publication number: 20190187376
    Abstract: A method for manufacturing a semiconductor structure and to a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.
    Type: Application
    Filed: July 27, 2017
    Publication date: June 20, 2019
    Inventors: Bich-Yen Nguyen, Gweltaz Gaudin
  • Patent number: 9905531
    Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: February 27, 2018
    Assignee: Soitec
    Inventors: Ionut Radu, Marcel Broekaart, Arnaud Castex, Gweltaz Gaudin, Gregory Riou
  • Patent number: 9818614
    Abstract: A method for bonding a first wafer onto a second wafer by molecular adhesion where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: November 14, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Gweltaz Gaudin
  • Patent number: 9548237
    Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement region. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: January 17, 2017
    Assignee: SOITEC
    Inventors: Gweltaz Gaudin, Oleg Kononchuk, Ionut Radu
  • Patent number: 9330958
    Abstract: The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 3, 2016
    Assignee: SOITEC
    Inventor: Gweltaz Gaudin
  • Publication number: 20150364364
    Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.
    Type: Application
    Filed: January 28, 2013
    Publication date: December 17, 2015
    Inventors: Gweltaz Gaudin, Oleg Kononchuk, Ionut Radu
  • Publication number: 20150348933
    Abstract: A method for bonding a first wafer on a second wafer by molecular adhesion where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.
    Type: Application
    Filed: August 7, 2015
    Publication date: December 3, 2015
    Inventor: Gweltaz Gaudin
  • Patent number: 9123631
    Abstract: A method for bonding a first wafer on a second wafer by molecular adhesion where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 1, 2015
    Assignee: SOITEC
    Inventor: Gweltaz Gaudin
  • Patent number: 9117686
    Abstract: The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as a bonding layer, on each substrate, at least one of the bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: August 25, 2015
    Assignee: SOITEC
    Inventor: Gweltaz Gaudin
  • Publication number: 20150179603
    Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa.
    Type: Application
    Filed: June 5, 2013
    Publication date: June 25, 2015
    Inventors: Ionut Radu, Marcel Broekaart, Arnaud Castex, Gweltaz Gaudin, Gregory Riou
  • Publication number: 20150132923
    Abstract: The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 14, 2015
    Inventor: Gweltaz Gaudin
  • Patent number: 8999090
    Abstract: The invention relates to a method for bonding two substrates, in particular, two semiconductor substrates that, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates. The gaseous flow is preferably a laminar flow that is essentially parallel to the bonding surfaces of the substrates, and has a temperature in a range of from room temperature up to 100° C.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: April 7, 2015
    Assignee: SOITEC
    Inventors: Gweltaz Gaudin, Fabrice Lallement, Cyrille Colnat, Pascale Giard