Patents by Inventor Gwo-Shii Yang

Gwo-Shii Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100084683
    Abstract: A light emitting diode (LED) package is provided. The LED package includes a carrier, a package housing, a strength enhancement structure, an ESD protector and an LED chip. The carrier has a first surface and a second surface. The carrier includes a first electrode and a second electrode, wherein a gap is between the first electrode and the second electrode. The package housing is disposed on the carrier and has a first aperture and a second aperture. The first surface is exposed by the first aperture while the second surface is exposed by the second aperture. The strength enhancement structure is disposed at the gap. The ESD protector is disposed on the carrier and located within the second aperture. The LED chip is disposed on the carrier and located within the first aperture, wherein the ESD protector and the LED chip is electrically connected to the carrier.
    Type: Application
    Filed: December 7, 2009
    Publication date: April 8, 2010
    Applicant: NOVALITE OPTRONICS CORP.
    Inventors: Kou-Rueh Lai, Gwo-Shii Yang, Kung-Chi Ho, Hu-Chen Tsai, Wen-Chuan Wang
  • Publication number: 20070194422
    Abstract: A Light Emitting Diode (LED) package including a carrier, a package housing, an LED chip, and an electrostatic discharge protector (ESD protector) is provided. The package housing encapsulates a part of the carrier so as to provide a chip-accommodating space on the carrier. The LED chip disposed on the carrier and located in the chip-accommodating space is electrically connected to the carrier. The ESD protector disposed on the carrier and encapsulated by the package housing is electrically connected to the carrier. The LED package has excellent light-emitting intensity, since the light emitted from the LED chip is not absorbed by the ESD protector encapsulated by the package housing. Additionally, a fabricating method of the LED package is also provided.
    Type: Application
    Filed: September 28, 2006
    Publication date: August 23, 2007
    Applicant: NOVALITE OPTRONICS CORP.
    Inventors: Kou-Rueh Lai, Gwo-Shii Yang, Kung-Chi Ho, Hu-Chen Tsai, Wen-Chuan Wang
  • Patent number: 6806182
    Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: October 19, 2004
    Assignees: International Business Machines Corporation, Infineon Technologies, AG, United Microelectronics Co.
    Inventors: Darryl Restaino, Shahab Siddiqui, Erdem Kaltalioglu, Delores Bennett, Chih-Chih Liu, Hsueh-Chung Chen, Tong-Yu Chen, Gwo-Shii Yang, Chiung-Sheng Hsiung
  • Patent number: 6750129
    Abstract: A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: June 15, 2004
    Assignee: Infineon Technologies AG
    Inventors: Gwo-Shii Yang, Jen Kon Chen, Hsueh-Chung Chen, Hans-Joachim Barth, Chiung-Sheng Hsiung, Chih-Chien Liu, Tong-Yu Chen, Yi-hsiung Lin, Chih-Chao Yang
  • Publication number: 20040092091
    Abstract: A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 13, 2004
    Inventors: Gwo-Shii Yang, Jen Kon Chen, Hsueh-Chung Chen, Hans-Joachim Barth, Chiung-Sheng Hsiung, Chih-Chien Liu, Tong-Yu Chen, Yi-hsiung Lin, Chih-Chao Yang
  • Publication number: 20030207559
    Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.
    Type: Application
    Filed: May 1, 2002
    Publication date: November 6, 2003
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Infineon Technologies North America Corp., United Microelectronics Co.
    Inventors: Darryl Restaino, Shahab Siddiqui, Erdem Kaltalioglu, Delores Bennett, C. C. Liu, Hsueh-Chung Chen, Tong-Yu Chen, Gwo-Shii Yang, Chiung-Sheng Hsiung
  • Patent number: 6583489
    Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: June 24, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Sung-Hsiung Wang, Yi-Min Huang, Gwo-Shii Yang, Chiung-Sheng Hsiung, Hsueh-Chung Chen, Chih-Chien Liu
  • Patent number: 6559004
    Abstract: A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: May 6, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Gwo-Shii Yang, Hsueh-Chung Chen, Chiung-Sheng Hsiung, Tong-Yu Chen, Sung-Hsiung Wang
  • Publication number: 20020176996
    Abstract: The present invention provides a method for electroplating. A substrate is provided with an opening and a metal layer is formed over the substrate and fills the opening. A cleaning solution including benzotriazole is used to clean the surface of the metal layer, while a protective layer is formed on the surface of the metal layer from reactions of benzotriazole with metal.
    Type: Application
    Filed: May 23, 2001
    Publication date: November 28, 2002
    Inventors: Hsueh-Chung Chen, Teng-Chun Tsai, Gwo-Shii Yang, Ming-Sheng Yang
  • Patent number: 6475865
    Abstract: A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: November 5, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Gwo-Shii Yang, Tri-Rung Yew, Coming Chen, Water Lur
  • Publication number: 20020155261
    Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.
    Type: Application
    Filed: April 24, 2001
    Publication date: October 24, 2002
    Inventors: Sung-Hsiung Wang, Yi-Min Huang, Gwo-Shii Yang, Chiung-Sheng Hsiung, Hsueh-Chung Chen, Chih-Chien Liu
  • Publication number: 20020155263
    Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.
    Type: Application
    Filed: March 25, 2002
    Publication date: October 24, 2002
    Applicant: United Microoelectronics Corp.
    Inventors: Sung-Hsiung Wang, Yi-Min Huang, Gwo-Shii Yang, Chiung-Sheng Hsiung, Hsueh-Chung Chen, Chih-Chien Liu
  • Patent number: 6316330
    Abstract: A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: November 13, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Gwo-Shii Yang, Tri-Rung Yew, Coming Chen, Water Lur
  • Patent number: 6306722
    Abstract: A method for fabricating, a shallow trench isolation structure. A pad oxide layer and a silicon nitride layer are formed in sequence on a substrate. A trench is formed in the substrate and a liner oxide layer is formed on a sidewall of the trench. A doped silicon dioxide layer is formed on the silicon nitride layer and fills the trench. An annealing process is performed to density the doped silicon dioxide layer. A portion of the doped silicon dioxide layer is removed to expose the silicon nitride layer by a planarization process.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: October 23, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Gwo-Shii Yang, Tri-Rung Yew, Coming Chen, Water Lur
  • Patent number: 6281143
    Abstract: A method for forming borderless contact is disclosed. The method includes providing a substrate with active areas and a trench isolation region in which the active areas are silcide. Then, the substrate is nitridized such that a titanium nitride layer is formed on the active areas and a silicon oxynitride is formed on the trench isolation region. A dielectric layer is deposited on the substrate and an opening is etched in the dielectric layer in which the opening overlies both a portion of the trench isolation region and a portion of the active area.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: August 28, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Michael W C Huang, Hsueh-Hao Shih, Gwo-Shii Yang, Tri-Rung Yew
  • Patent number: 6254676
    Abstract: A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: July 3, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Gwo-Shii Yang, Michael W C Huang, Chien Chao Huang, Hsien-Ta Chung, Tri-Rung Yew
  • Patent number: 6251783
    Abstract: A method of manufacturing shallow trench isolation structures. The method includes the steps of depositing insulating material into the trench of a substrate to form an insulation layer. The substrate has a plurality of active regions, each occupying a different area and having different sizes. In addition, there is a silicon nitride layer on top of each active region. Thereafter, a photoresist layer is then deposited over the insulation layer. Next, a portion of the photoresist layer is etched back to expose a portion of the oxide layer so that the remaining photoresist material forms a cap layer over the recessed area of the insulation layer. Subsequently, using the photoresist cap layer as a mask, the insulation layer is etched to remove a portion of the exposed oxide layer, thereby forming trenches within the oxide layer. After that, the photoresist cap layer is removed.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: June 26, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Tri-Rung Yew, Kuo-Tai Huang, Gwo-Shii Yang, Water Lur
  • Patent number: 6249138
    Abstract: A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: June 19, 2001
    Assignees: United Microelectronics Corp., United Silicon Incorporated
    Inventors: Michael WC Huang, Gwo-Shii Yang, Hsiao-Ling Lu, Wen-Yi Hsieh
  • Patent number: 6248644
    Abstract: A method of fabricating a shallow trench isolation structure is described. A preserve layer is formed on a substrate. A trench is formed in the substrate and the preserve layer. An oxide layer is formed over the substrate to fill the trench. A wet densification step is performed in a moist environment. A planarization step is performed until the preserve layer is exposed. A shallow trench isolation structure is formed.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: June 19, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Gwo-Shii Yang, Hsueh-Hao Shih, Chih-Chien Liu, Tri-Rung Yew
  • Patent number: 6238989
    Abstract: A process of forming a silicide on a source/drain region of a MOS device is described, wherein the MOS device has a gate spacer partially covering the source/drain region. A silicon film is formed on the source/drain region, wherein the silicon film has a portion near the gate spacer substantially thinner than the other portion of the silicon film. The silicon film is reacted with a metal film to wholly consume the portion of the silicon film near the gate spacer and to partially consume the other portion of the silicon film.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: May 29, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Michael Wc Huang, Gwo-Shii Yang, James CC Huang, Wen-Yi Hsieh