Abstract: A method of fabricating a shallow trench isolation structure is described. A mask layer is formed on the substrate. The mask layer and the substrate are patterned to form trenches in the substrate. The trenches comprise a smallest trench. A first isolation layer is formed on the mask layer to fill partially the trenches. A densification step is performed. A second isolation layer is formed on the first isolation layer to fill completely the trench. The first isolation layer and the second isolation layer are removed until the mask layer is exposed. The mask layer is removed.

Abstract: A method of fabricating a DRAM capacitor includes the step of forming an insulated layer and an etching stop layer successively on a substrate having a device structure. A contact window is formed within the etching stop layer and the insulated layer. A conductive layer is formed on the etching layer to fill in the contact window and patterned to serve as a lower electrode of the capacitor. A highly doped dielectric layer is then formed on the lower electrode and a thermal process is performed to diffuse the dopants inside the highly doped dielectric layer into the surface of the lower electrode. The dielectric layer is removed. A capacitor dielectric layer and an upper electrode are successively formed on the lower electrode to complete the fabrication of the capacitor.

Abstract: The present invention relates to a method of forming a contact hole of a DRAM on the semiconductor wafer. The semiconductor wafer comprises a substrate, a first dielectric layer, two bit lines on the first dielectric layer, a second dielectric layer, and a photo-resist layer comprising an opening to define the pattern of the contact hole. The method comprises performing a first anisotropic etching process to vertically remove a portion of the two dielectric layers and two bit lines to grossly form the contact hole, removing the photo-resist layer in its entirety, performing a thermal oxidation to form a silicon oxide layer on the side walls of the two bit lines, then forming a silicon nitride layer on the surface of the contact hole, and performing a dry etching to remove the silicon nitride layer. There is a silicon oxide layer and a silicon nitride layer between the bit line and the contact hole, and the contact area of the contact hole will not be reduced.

Abstract: An improved method for forming shallow trench isolation structure is described. The present method comprises the steps of providing a pad oxide layer and a mask layer on a semiconductor substrate and forming a trench structure therein. Next, a liner oxide layer is formed on the surface of the trench structure in the semiconductor substrate and is extensively formed on the side surface of the mask layer exposed therein and the top surface of the mask layer by wet oxidation. A dielectric material is deposited on the liner oxide layer and fills the trench structure. The dielectric material layer is planarized. The mask layer and the pad oxide layer are then removed to form the isolation structures. The method for forming the shallow trench structures on a semiconductor structure in accordance with the present invention can eliminate the kink effect that occurs in the conventional method.

Abstract: A method of fabricating shallow trench isolation (STI) forms a trench in a substrate and a liner oxide layer in the trench. A first high density plasma chemical vapor deposition (HDPCVD) is performed to form a conformal oxide layer on the liner oxide layer, without applying bias to the substrate. A second HDPCVD is then performed to form an oxide layer that fills the trench and covers the conformal oxide layer on the conformal oxide layer.

Abstract: A method for manufacturing shallow trench isolation structure includes the steps of fabricating a self-aligned silicon nitride mask over the trench region so that a kink effect due to the misalignment of mask during a conventional mask-making process can be avoided. Moreover, the silicon nitride mask requires fewer steps and less complicated operations to construct than a conventional reverse tone mask.

Abstract: A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure with a rounded corner in integrated circuits through a rapid thermal process (RTP). In the fabrication of the STI structure, a sharp corner is often undesirably formed. This sharp corner , if not eliminated, causes the occurrence of a leakage current when the resultant IC device is in operation that significantly degrades the performance of the resultant IC device. To eliminate this sharp corner , an RTP is performed at a temperature of above 1,100.degree. C., which temperature is higher than the glass transition temperature of the substrate, for about 1 to 2 minutes. The result is that the surface of the substrate is oxidized into an sacrificial oxide layer and the sharp corner is deformed into a rounded shape with a larger convex radius of curvature. This allows the problems arising from the existence of the sharp corner to be substantially eliminated.