Abstract: Provided are a vehicle sensor cleaning apparatus and a control method thereof. The vehicle sensor cleaning apparatus includes a liquid sprayer configured to spray washer fluid on at least one sensor arranged in a vehicle, an air sprayer configured to spray air on the at least one sensor, a liquid controller configured to control washer fluid spraying of the liquid sprayer, and an air controller configured to control air spraying of the air sprayer.

Abstract: A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high

Abstract: A display device includes a first substrate and a second substrate facing each other; and a filling layer disposed between the first substrate and the second substrate. The first substrate comprises a support substrate comprising a display area in which emission areas associated with sub-pixels, are arranged; a light-emitting element layer disposed on one surface of the support substrate; and an encapsulation layer disposed on the light-emitting element layer. The encapsulation layer comprises a first inorganic layer covering the light-emitting element layer; an organic layer disposed on the first inorganic layer and overlapping the light-emitting element layer; and a second inorganic layer disposed on the first inorganic layer and covering the organic layer. A thickness of the first inorganic layer is smaller than a thickness of the second inorganic layer.

Abstract: Various embodiments generally relate to a power distribution network and a semiconductor device, which may include: a plurality of chip pads; a first distribution layer in which a plurality of first conductive lines having rectangular shapes of different sizes, respectively, are disposed; a second distribution layer in which a plurality of second conductive lines including a central cross-shaped conductive line and L-shaped conductive lines open toward respective corners of the second distribution layer are disposed; and a redistribution layer electrically coupling chip pads to which power is applied among the plurality of chip pads and the first conductive lines of the first distribution layer.

Abstract: A cleaning apparatus including a vacuum cleaner and a docking station is provided. The cleaning apparatus includes a vacuum cleaner including a dust collecting chamber in which foreign substances are collected, and a docking station configured to be connected to the dust collecting chamber to remove the foreign substances collected in the dust collecting chamber. The dust collecting chamber is configured to collect foreign substances through centrifugation, and configured to be docked to the docking station, and the docking station includes a suction device configured to suction the foreign substances and air in the dust collecting chamber docked to the docking station.

Abstract: Provided is a heating unit including: a heating plate for heating a substrate; a heater installed in the heating plate; and a control unit for controlling the heater, in which wherein the heater includes: a first heater; and a second heater installed at a position different from a position of the first heater, and the control unit includes: a power source for transferring power to at least one of the first heater and the second heater; and a switching module for connecting the first heater and the second heater in series or connecting the first heater and the second heater in parallel.

Abstract: An apparatus for treating a substrate is disclosed. The apparatus for treating the substrate includes a housing having a treatment space inside the housing, a plate to support the substrate inside the housing, a heating member provided inside the plate to heat the substrate and including a plurality of heating zones, a temperature measuring member to measure a temperature of the substrate with respect to each of the plurality of heating zones of the heating member, and a control unit to control a temperature for the heating member in a dynamic section of a temperature change graph measured in the temperature measuring member. The control unit performs temperature control with respect to each of the plurality of heating zones of the heating member to uniformize the thickness of the thin film on the substrate.

Abstract: An apparatus for treating a substrate is disclosed. The apparatus for treating the substrate includes a housing having a treatment space inside the housing, a plate to support the substrate inside the housing, a heating member provided inside the plate to heat the substrate and including a plurality of heating zones, a temperature measuring member to measure a temperature of the substrate with respect to each of the plurality of heating zones of the heating member, and a control unit to control a temperature for the heating member in a dynamic section of a temperature change graph measured in the temperature measuring member. The control unit performs temperature control with respect to each of the plurality of heating zones of the heating member to uniformize the thickness of the thin film on the substrate.

Abstract: A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

Abstract: A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

Abstract: A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

Abstract: A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a lower electrode disposed on the semiconductor substrate wherein an upper surface of the lower electrode has a recess, an interlayer insulating layer disposed on the semiconductor substrate and the lower electrode, the interlayer insulating layer including a variable resistive region exposing the upper surface of the lower electrode, and a variable resistive layer filled in the variable resistive region that contacts the recess of the lower electrode. The variable resistive layer is formed to have an increased width toward a top and a bottom thereof.

Abstract: A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction.

Abstract: The present invention provides an etching composition, comprising a silyl phosphate compound, phosphoric acid and deionized water, and a method for fabricating a semiconductor, which includes an etching process employing the etching composition. The etching composition of the invention shows a high etching selectivity for a nitride film with respect to an oxide film. Thus, when the etching composition of the present invention is used to remove a nitride film, the effective field oxide height (EEH) may be easily controlled by controlling the etch rate of the oxide film. In addition, the deterioration in electrical characteristics caused by damage to an oxide film or etching of the oxide film may be prevented, and particle generation may be prevented, thereby ensuring the stability and reliability of the etching process.

Abstract: A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction.

Abstract: A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction.

Abstract: A method for fabricating a semiconductor device includes forming a multilayer, forming a plurality of patterns by etching the multilayer and a portion of the substrate, forming a supporter to support the plurality of patterns, and removing residues formed during the etching.

Abstract: A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on an interface between the metal layer and the barrier metal layer.