Abstract: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

Abstract: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair.

Abstract: A scheme for reducing jitter in high-speed digital communication by adaptively controlling the loop bandwidth of a receiver PLL to reduce the relative jitter between the recovered data and clock. The scheme uses phase pointer activity to represent the relative jitter. The phase pointer activity is measured and used to control the receiver PLL loop bandwidth. The receiver PLL loop bandwidth is repeatedly incremented or decremented by a step size based on the comparison between a newly measured activity value and the old activity value, until the phase pointer activity reaches a minimum. Because the PLL performance requirement of the transmitter can be relaxed, compatibility with legacy transmitters and multi-vendor transmitters is enhanced. Because tight control of fabrication process parameters of PLLs may be relaxed, the fabrication yield may also be improved.

Abstract: Logic gates are provided that include a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) to produce a gate threshold voltage that differs from a mid-supply voltage level, while providing symmetry in the switching transients of the output logic signals. In one embodiment, the logic gate is a NAND gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level. In another embodiment, the logic gate is a NOR gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level.

Abstract: Methods and circuits for measuring clock phase uniformity of multi-phase clock set, including by generating at least one DC phase difference signal such that the DC phase difference signal is, or the DC phase difference signals are, indicative of the phase difference between the clocks of each of multiple pairs of clocks of the clock set, and methods and circuitry for generating such DC phase difference signals. Preferably, multiplexer circuitry asserts to DC signal generation circuitry any selected one of a number of pairs of clocks of the clock set, and the DC signal generation circuitry includes logic (for generating a binary signal in response to each clock pair) and a low pass filter for generating a DC phase difference signal in response to the binary signal. Other aspects are receivers and transmitters that include circuitry for generating at least one DC phase difference signal, and systems including at least one such transmitter (or receiver) and a link (e.g.

Abstract: A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.

Abstract: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair.

Abstract: A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.

Abstract: The present invention relates to a serial interface transmission system with more than one data line, in which the transmitted data has in-band and out-of-band characters. More particularly, the present invention relates to methods and systems for sending side channel data over a high-speed digital communications link, e.g., a video link. One embodiment of the invention provides a high-speed digital transmitter capable of sending side channel data. The transmitter includes a channel zero encoder, a multiplexer, data enable out (DEout) control logic, and a channel one encoder. The channel one encoder receives input from the channel one multiplexer and the channel one DEout control logic. Another embodiment of the invention provides a high-speed digital receiver capable of receiving side channel data. The receiver includes a channel zero decoder, a channel one decoder, DEI signal and FIFO control signal recovery logic, and a channel one de-multiplexer.

Abstract: A system and method for measuring and utilizing a pseudo pixel error rate in digital data transmission is disclosed. As an alternative to measuring actual pixel error rate measurement, the present invention uses a pseudo pixel error rate detection scheme where the errors occurred in the special character patterns used in data encoding are measured. A particular embodiment uses a de-glitch filter for filtering the glitches from an unfiltered data enable (DE), a delay for delaying the unfiltered DE to match the delay of the de-glitch filter, and a comparator for comparing the unfiltered DE and the filtered DE to determine the occurrence of an error. It further includes a counter to count the errors occurred.

Abstract: In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal.

Abstract: A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information.

Abstract: A serial data transmission system in which a transmitter encodes data in accordance with a TMDS-like encoding algorithm and transmits the TMDS-like encoded data over a serial link to a receiver. The encoded data are transmitted as a run length limited (“RLL”) code word sequence, including transition-minimized code words. In some embodiments, the RLL code word sequence includes only Min words, including both DC balancing Min words and DC unbalancing Min words. In other embodiments, the RLL code word sequence includes both transition-maximized code words and transition-minimized code words. Other aspects of the invention are circuitry and methods for TMDS-like encoding of data for transmission as an RLL code word sequence.

Abstract: The present invention is directed to systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of: a) performing transition controlled encoding of a first sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to produce masked n+1 bit data characters; c) DC balancing the masked n+1 bit data characters to produce DC balanced, masked n+2 bit data characters; d) scrambling the DC balanced, masked n+2 bit data characters using a scrambling formula to produce encrypted n+2 bit data characters; e) encoding control data into encoded n+2 bit control characters, f) generating a serial data stream in response to the encrypted data characters and encoded control characters, and g) transmitting the serial data stream over a communication link.

Abstract: A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (“VCO”) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e.g., a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.

Abstract: Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.

Abstract: A voltage controlled oscillator (“VCO”) circuit capable of generating signals with reduced jitter and/or low-phase noise is provided. One embodiment provides a plurality of cascaded VCO cells, where each VCO cell can include a source coupled differential pair, a bias transistor connected to the differential pair for biasing the differential pair, a resistive load pair connected to the differential pair, and a voltage controlled capacitor pair or varactor pair connected to the differential pair. The varactors provide control over the frequency of the oscillations produced by the VCO circuit in combination with a control voltage. A phase frequency detector combined with a charge pump and loop filter provide the control voltage.

Abstract: A new spread spectrum phase modulation (SSPM) technique is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.

Abstract: New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a receiver with external termination. Furthermore, the communication system may include a phase tracker and a frame aligner. The phase tracker continously monitors the most frequent transition edges in the oversampled data so that the phase of the receiver clock keeps track of the sender clock. The frame aligner comprises a comma detector which enables instant synchronization of data words with a single comma character within a serial data stream.

Abstract: A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.