Abstract: A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. An oxide layer is formed over the implanted portion of the polysilicon layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.

Abstract: An improved method for planarizing an interlevel dielectric comprising two chemical mechanical polish steps. After an interlevel dielectric containing a topographical valley between a pair of topographical peaks is formed, the dielectric is chemically-mechanically polished in a first polish step at a first force using a first polish pad having a first rigidity to round the sharp dielectric corners or edges that exist at the transition between the peaks and valleys. After the first polish step has rounded the edges, a second polish step is performed with a second polish pad of second rigidity. The second polish pad is more rigid than the first polish pad and the second force is greater than the first. The second polish steps uses a high viscosity slurry to reduce slurry turnover in the regions proximate to the dielectric valleys thereby reducing the chemical etching in the valleys and improving the planarization efficiency.

Abstract: A semiconductor fabrication process in which nitrogen is incorporated into the transistor gate without significantly increasing the resistivity of the source/drain region. The incorporation of nitrogen into the gate structure substantially reduces the migration of impurity dopants from the silicon gate into the transistor channel region resulting in a more stable and reliable transistor. In one embodiment, a tail of the nitrogen impurity distribution incorporated into the gate structure extends into the channel region of the semiconductor substrate. In this embodiment, the nitrogen within the channel region prevents excessive lateral diffusion of source/drain impurities thereby permitting the fabrication of deep sub-micron transistors.

Abstract: An amorphized implant is performed to retard diffusion of ions in the source and drain regions. By retarding the diffusion of ions in these regions, a shallower junction is advantageously created in the silicon regions of the wafer. A slight degradation in leakage current is obtained if the amorphized implant is performed on both the source and the drain sides of a transistor. However, since the source region is a low voltage region with a very shallow junction, MOSFETs in both n-channel and p-channel regions are formed with improved performance and reliability.A method of fabricating an integrated circuit includes forming a gate electrode over a semiconductor substrate, forming a source mask extending over the drain region of the semiconductor substrate, and implanting an implant species into the source region of the semiconductor substrate to form an amorphous implant layer of the semiconductor substrate.

Abstract: An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface.

Abstract: Diffusion of dopants within the gate of the transistor and/or the source/drain regions can be inhibited by the ion co-implantation of impurities in addition to the ion implantation of the n-type or p-type dopants. Implanting a combination of nitrogen and carbon for p-type devices in addition to the p-type dopants and implanting a combination of nitrogen and fluorine for n-type devices in addition to the n-type dopants, significantly reduces the diffusion of the n-type and p-type dopants. The co-implantation of the additional impurities may be performed before patterning of the polysilicon layer to yield the gate conductors. The impurities may be implanted first, followed by the n-type or p-type dopants. Additional implantation of the impurities may be performed after the patterning of the polysilicon layer in order to reduce dopant diffusion in the source and drain regions.

Abstract: A method of making N-channel and P-channel devices using separate drive-in steps is disclosed. The method includes providing a semiconductor substrate with first and second active regions, introducing a first dopant into the first active region to provide all doping for a source and a drain in the first active region, driving-in the first dopant to form the source and the drain in the first active region, introducing a second dopant into the second active region to provide all doping for a source and a drain in the second active region after driving-in the first dopant, and driving-in the second dopant to form the source and the drain in the second active region. Preferably, the first dopant is arsenic or phosphorus, the second dopant is boron, and the first temperature exceeds the second temperature by at least 50.degree. C. In this manner, the boron need not be subjected to the higher first temperature, thereby reducing boron diffusion.

Abstract: A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact.

Abstract: A gate conductor structure and method for forming the structure are provided whereby the overall gate length can be made with less susceptibility to lithography variations. The gate conductor is produced by defining a sidewall surface region and then forming the gate conductor material on that sidewall surface a closely controlled, defined lateral distance therefrom. The gate conductor length is therefore dependent primarily upon deposition technology rather than both deposition and lithography. Deposition can be controlled at the defined sidewall surface more closely than mask alignment, thin film development and etching processes of conventional designs. The gate conductor is formed from the sidewall surface such that the sidewall surface demonstrates a greater likelihood of forming a thicker sidewall spacer on one surface of the gate conductor than the opposing gate conductor surface.

Abstract: A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. A silicide layer is formed upon the upper surface of the exposed polysilicon layer. An oxide layer is formed over the silicide layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.

Abstract: A process is provided for forming a trench isolation structure which includes dielectric spacers composed of a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. In an embodiment, a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner which is incorporated with nitrogen atoms is thermally grown upon the sidewalls and base of the trench. A layer of low K dielectric material is deposited across the oxide liner and the masking layer. The dielectric material is anisotropically etched to form sidewall spacers upon the oxide liner. A fill oxide is then formed within the trench upon the sidewall spacers and the oxide liner. The resulting trench isolation structure includes a low K dielectric material interposed between an oxide liner and a fill oxide.

Abstract: Transistor drive current is controlled by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter. Integrated circuit parameters upon which the light exposure is varied include gate oxide thickness, rapid temperature annealing (RTA) temperature, polyetch bias and the like.

Abstract: A semiconductor process for forming a gate electrode of an MOS transistor. A gate dielectric is deposited on an upper surface of a semiconductor substrate. A dielectric constant of the gate dielectric layer is in the range of approximately 25 to 300. A thickness of the gate dielectric is in the range of approximately 50 to 1,000 angstroms. A conductive gate layer is then formed on the gate dielectric layer. A first nitrogen distribution is then introduced into the gate dielectric layer. The introduction of the first nitrogen distribution is typically accomplished by implanting a first nitrogen bearing species into the gate dielectric layer. Ideally, a peak impurity concentration of the first nitrogen distribution is located at an interface between the semiconductor substrate and the gate dielectric layer. Thereafter, a second nitrogen distribution is introduced into the gate dielectric layer.

Abstract: An integrated circuit fabrication method incorporating nitrogen into the polysilicon-dielectric interface in an MOS transistor. A semiconductor substrate having a P-well region and an N-well region is provided. Each well region includes channel regions and source/drain regions. A dielectric layer, preferably a thermal oxide, is formed on an upper surface of the semiconductor substrate. The thermal oxide can be grown in a nitrogen bearing ambient, an O.sub.2 ambient, or an H.sub.2 O ambient. Alternatively, the dielectric may be formed from a deposited oxide. Thereafter, a layer of polysilicon is formed on the dielectric layer and a plurality of "nitrogenated" polysilicon gates is formed on the dielectric layer over the channel regions. In a presently preferred embodiment, nitrogen species are introduced into the polysilicon gates with an ion implantation step. The nitrogen implantation step may alternatively be performed before or after the patterning of the polysilicon layer.

Abstract: An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide.

Abstract: A transistor with a buried insulative layer beneath a channel region is disclosed. Unlike conventional SIMOX, the buried insulative layer has a top surface beneath the channel region that is closer than bottom surfaces of the source and drain to the top surface of the substrate. Preferably, the buried insulative layer is formed by implanting oxygen into the substrate and then performing a high-temperature anneal so that the implanted oxygen reacts with silicon in the substrate to form a continuous stoichiometric layer of silicon dioxide. Advantageously, the buried insulative layer provides a diffusion barrier and an electrical isolation barrier for the channel region.

Abstract: A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region.

Abstract: A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, the first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.

Abstract: A detached drain transistor including a semiconductor substrate, a source impurity distribution, a drain impurity distribution, a gate dielectric, and a conductive gate. The source impurity distribution is substantially contained within a source region of the semiconductor substrate. The drain impurity distribution is substantially contained within a detached drain region of the semiconductor substrate. The gate dielectric is formed on an upper surface of the semiconductor substrate. The conductive gate is formed on the gate dielectric and laterally disposed over a channel region of the semiconductor substrate. The channel region extends laterally between the source region of the semiconductor substrate and the detached drain region. The channel boundary of the detached drain region is laterally displaced from a first sidewall of the conductive gate by a detached displacement. Preferably, the gate dielectric is a thermal oxide having a thickness of approximately 20 to 200 angstroms.

Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second active region. A first dielectric layer is then formed on said trench and a polysilicon layer is deposited on said first dielectric layer. The polysilicon layer is then thermally oxidized to form a second dielectric layer. Preferably the first dielectric is a thermal oxide 40 to 500 angstroms in thickness consuming less than 200 angstroms of said first active region and said second active region. The polysilicon layer is preferably between 1000 to 2000 angstroms.