Abstract: One method of forming a semiconductor device includes forming a gate electrode on a substrate and then forming a spacer adjacent to a sidewall of the gate electrode. An active region is formed in the substrate adjacent to the spacer and spaced apart from the gate electrode using a first dopant material of a first conductivity type. A protecting layer is formed over the active region and adjacent to the spacer. At least a portion of the spacer is then removed to form an opening between the protecting layer and the gate electrode. In some instances, the spacer may be formed by independent deposition of two different materials (e.g., silicon nitride and silicon dioxide), one of which can be selectively removed with respect to the other. A lightly-doped region is formed in the substrate adjacent to the gate electrode using a second dopant material of the first conductivity type.

Abstract: During a semiconductor substrate ion implant process thermal energy is supplied to raise the temperature of the semiconductor wafer. The increased temperature of the semiconductor wafer during implantation acts to anneal the implanted impurities or dopants in the wafer, reducing impurity diffusion and reducing the number of fabrication process steps. An ion implant device includes an end station that is adapted for application and control of thermal energy to the end station for raising the temperature of a semiconductor substrate wafer during implantation. The adapted end station includes a heating element for heating the semiconductor substrate wafer, a thermocouple for sensing the temperature of the semiconductor substrate wafer, and a controller for monitoring the sensed temperature and controlling the thermal energy applied to the semiconductor substrate wafer by the heating element.

Abstract: An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.

Abstract: The present invention is directed to a semiconductor device having an ultra thin gate oxide and a method for making same. The method is comprised of implanting nitrogen into a region of a semiconducting substrate, and forming a gate dielectric above the region in the substrate. The method further comprises forming a gate conductor above the gate dielectric and forming at least one source/drain region. The present invention is also directed to a transistor having a gate dielectric positioned above a surface of a semiconducting substrate, the gate dielectric being comprised of a nitrogen bearing oxide having a nitrogen concentration ranging from approximately 4-8%. The transistor further comprises a gate conductor positioned above the gate dielectric and at least one source/drain region.

Abstract: An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.

Abstract: A method is provided for fabricating a semiconductor device, the method including forming a first dielectric layer above a structure and forming an island of a sacrificial layer above the first dielectric layer. The method also includes introducing a first dopant into first portions of the structure, leaving a second portion of the structure protected by the island, and removing first portions of the island leaving a second portion of the island. The method further includes introducing a second dopant into the first portions and third portions of the structure, leaving a fourth portion of the structure protected by the second portion of the island. The method additionally includes forming a second dielectric layer adjacent the second portion of the island, removing the second portion of the island, forming a gate dielectric above the fourth portion of the structure and forming a gate conductor above the gate dielectric.

Abstract: A transistor and a transistor fabrication method are presented where a sequence of spacers are formed and partially removed upon sidewall surfaces of the gate conductor to produce a graded junction having a relatively smooth doping profile. The spacers include removable and non-removable structures formed on the sidewall surfaces. The adjacent structures have dissimilar etch characteristics compared to each other and compared to the gate conductor. A first dopant (MDD dopant) and a second dopant (source/drain dopant) are implanted into the semiconductor substrate after the respective formation of the removable structure and the non-removable structure. A third dopant (LDD dopant) is implanted into the semiconductor substrate after the removable layer is removed from between the gate conductor and the non-removable structure (spacer). As a result a graded junction is created having higher concentration regions formed outside of lightly concentration regions, relative to the channel area.

Abstract: An integrated circuit fabrication process is provided for using a dual salicidation process to form a silicide gate conductor to a greater thickness than silicide structures formed upon source and drain regions of a transistor. A high K gate dielectric residing between the gate conductor and the substrate substantially inhibits consumption of the junctions during the formation of the silicide gate conductor. In an embodiment, a relatively thick layer of refractory metal is deposited across a transistor arranged upon and within a silicon-based substrate. The transistor includes a polysilicon gate conductor arranged upon a portion of a high K gate dielectric interposed between a pair of source and drain junctions. The refractory metal is heated to convert the polysilicon gate conductor to a silicide gate conductor.

Abstract: An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls.

Abstract: A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film.

Abstract: A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and an extended silicide layer is formed over the polysilicon line. The extended silicide layer may be formed by forming a patterned metal layer over the polysilicon line, forming a polysilicon layer over the patterned metal layer, and reacting the patterned metal layer with the polysilicon layer to form the extended silicide layer over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the silicide layer may extend over the top of the second polysilicon line and interconnects the two polysilicon lines.

Abstract: A semiconductor manufacturing process is provided in which an oxidation retarding species is introduced into regions of the substrate distal from the isolation structures. A subsequent thermal oxidation process results in the formation of a gate dielectric film in which the film thickness proximal to the isolation structures is greater than the film thickness distal from the isolation structures. Broadly speaking, an isolation structure is formed in an isolation region of a semiconductor substrate. A mask is then formed on an upper surface of the semiconductor substrate. The mask covers the isolation structure and portions of the semiconductor substrate proximal to the isolation structure. A nitrogen bearing impurity distribution is then introduced into portions of the semiconductor substrate exposed by the mask. The nitrogen bearing impurity distribution therefore substantially resides within portions of the semiconductor substrate distal from the isolation structures.

Abstract: A semiconductor process in which a first nitrogen bearing oxide is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then formed on the nitrogen bearing oxide. The first oxide and the silicon nitride layer are then patterned to expose an upper surface of the substrate over a trench region of the substrate. An isolation trench is then etched into the trench region of the substrate and a nitrogen bearing liner oxide is then formed on sidewalls and a floor of the trench. An isolation dielectric is then formed within the trench and, thereafter, the silicon nitride layer is removed from the wafer. A suitable thickness of the first nitrogen bearing oxide and of the liner oxide is in the range of approximately 30 to 100 angstroms. A consumption of adjacent active regions caused by the thermal oxidation process is preferably less than approximately 50 angstroms.

Abstract: An integrated circuit and a method of fabricating the same in a substrate are provided. A trench is formed in the substrate. The trench has a sidewall. A first insulating layer is formed on the sidewall. A gate electrode is formed on the first insulating layer. A first source/drain region is formed in the substrate and a second source/drain region is formed in the substrate. A first portion of the first source/drain region and a second portion of the second source/drain region are vertically spaced apart to define a channel region in the substrate. The process enables channel lengths to be set independent of the maximum resolution of the photolithographic system used to pattern the wafer. Very short channel lengths may be implemented.

Abstract: A fabrication process is provided that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact.

Abstract: A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.

Abstract: A process for making a high performance MOSFET with a scaled gate electrode thickness. In one embodiment, the process comprises first providing a substrate. A gate dielectric layer is formed on the substrate, and a gate electrode is formed on the gate dielectric layer. A middle portion of the gate electrode has a first height, and side portions of the gate electrode have heights that are less than the first height. A dopant species is implanted at a first energy level and at a first concentration, whereby lightly doped drain regions are formed in the substrate below the side portions of the gate electrode.

Abstract: A semiconductor device having a reduced polysilicon gate electrode width is provided along with a process for manufacturing such a device. In accordance with the present invention, a semiconductor device may be formed by forming an oxidation-resistant barrier layer over a substrate. At least one polysilicon block is formed over the barrier layer. A dopant is implanted through the barrier layer into the substrate. The polysilicon block is oxidized to grow an oxide layer on exposed surfaces and thereby reduce the width of the block. The oxide layer then can be removed to form a gate electrode having a reduced width. Plural implantations and oxidation-removal can be carried out as desired.

Abstract: A process is provided for forming dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate.

Abstract: A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and LDD regions formed that are self-aligned to both the gate electrode and the trench side-walls. A dielectric spacer is formed adjacent the gate electrode and extending to the trench side-walls. In this manner, the spacers essentially cover the LDD regions. Source and drain regions are formed that are adjacent the trench side-walls wherein the spacer serves to protect at least a portion of the LDD regions to maintain a spacing of the S/D regions from the gate electrode edge. In this manner an advantageously lowered E.sub.M provided by LDD regions is maintained. In some embodiments of the present invention, S/D regions are formed by implantation through the trench side-walls.