Abstract: A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit lines is substantially shorter than the length of the global digit lines. As a result, the local digit lines have substantially less capacitance so that a voltage stored by a memory cell capacitor can be more easily transferred to the local digit line. The coupling circuits provide current amplification so that the voltage on the local digit lines can be more easily transferred to the global digit lines. A write back circuit is coupled to the local digit line to restore the voltage of the memory cell capacitor.

Abstract: Compounds and methods related to NIR molecular imaging, in-vitro and in-vivo functional imaging, therapy/efficacy monitoring, and cancer and metastatic activity imaging. Compounds and methods demonstrated pertain to the field of peripheral benzodiazepine receptor imaging, metabolic imaging, cellular respiration imaging, cellular proliferation imaging as targeted agents that incorporate signaling agents.

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Abstract: The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench.

Abstract: The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically insulative material received laterally about the sidewalls of the projecting pillars. Openings are formed within a second material to the pillars. The pillars are etched from the substrate through the openings in the second material, and individual capacitor electrodes are formed within the openings in electrical connection with the storage node locations. The individual capacitor electrodes have the anisotropically etched insulative material received laterally about their outer sidewalls. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other implementations and aspects are contemplated.

Abstract: The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a substrate. Individual of the capacitor electrode openings are bounded on a first pair of opposing sides by a first capacitor electrode-forming material at one elevation and on a second pair of opposing sides by a different second capacitor electrode-forming material at the one elevation. Individual capacitor electrodes are formed within individual of the capacitor electrode openings. The capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

Abstract: A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the access transistors selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.

Abstract: An immersion photolithography system includes a lens system positioned to focus radiation emitted from the radiation source onto a workpiece or wafer on a stage. A liquid supply system provides liquid between the lens of the lens system closest to the wafer. A seal element encloses a volume of liquid which keeps the lower or wetted surface of the lens wet. The seal element may be located at a lens parking location adjacent to the stage. The system provides an improved way for keeping the lens wet between exposure processing.

Abstract: The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a substrate. Individual of the capacitor electrode openings are bounded on a first pair of opposing sides by a first capacitor electrode-forming material at one elevation and on a second pair of opposing sides by a different second capacitor electrode-forming material at the one elevation. Individual capacitor electrodes are formed within individual of the capacitor electrode openings. The capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

Abstract: The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on a substrate. A patterned masking layer is formed over the metal. The patterned masking layer comprises openings therethrough to an outer surface of the metal. Individual of the openings are received over individual of the capacitor storage node locations. A pit is formed in the metal outer surface within individual of the openings. After forming the pits, the metal is anodically oxidized through the openings effective to form a single metal oxide-lined channel in individual of the openings over the individual capacitor storage nodes. Individual capacitor electrodes are formed within the channels in electrical connection with the individual capacitor storage node locations. At least some of the metal oxide is removed from the substrate, and the individual capacitor electrodes are incorporated into a plurality of capacitors.

Abstract: A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit lines is substantially shorter than the length of the global digit lines. As a result, the local digit lines have substantially less capacitance so that a voltage stored by a memory cell capacitor can be more easily transferred to the local digit line. The coupling circuits provide current amplification so that the voltage on the local digit lines can be more easily transferred to the global digit lines. A write back circuit is coupled to the local digit line to restore the voltage of the memory cell capacitor.

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Abstract: A method of forming contacts used in a memory device. The method involves forming a via in an insulating layer, forming spacers on sidewalls of the via, and filling the via with a conductive material. The resulting contact has rounded upper corners to improve the reliability of the memory device. Also disclosed is a subsequent recessing and refilling method to mitigate keyholes in the memory device contacts.

Abstract: The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on a substrate. A patterned masking layer is formed over the metal. The patterned masking layer comprises openings therethrough to an outer surface of the metal. Individual of the openings are received over individual of the capacitor storage node locations. A pit is formed in the metal outer surface within individual of the openings. After forming the pits, the metal is anodically oxidized through the openings effective to form a single metal oxide-lined channel in individual of the openings over the individual capacitor storage nodes. Individual capacitor electrodes are formed within the channels in electrical connection with the individual capacitor storage node locations. At least some of the metal oxide is removed from the substrate, and the individual capacitor electrodes are incorporated into a plurality of capacitors.

Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

Abstract: The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically insulative material received laterally about the sidewalls of the projecting pillars. Openings are formed within a second material to the pillars. The pillars are etched from the substrate through the openings in the second material, and individual capacitor electrodes are formed within the openings in electrical connection with the storage node locations. The individual capacitor electrodes have the anisotropically etched insulative material received laterally about their outer sidewalls. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other implementations and aspects are contemplated.

Abstract: The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes anodically etching individual capacitor electrode channels within a material over individual capacitor storage node locations on a substrate. The channels are at least partially filled with electrically conductive capacitor electrode material in electrical connection with the individual capacitor storage node locations. The capacitor electrode material is incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.