Abstract: A method for arranging nanotube elements within nanotube fabric layers and films is disclosed. A directional force is applied over a nanotube fabric layer to render the fabric layer into an ordered network of nanotube elements. That is, a network of nanotube elements drawn together along their sidewalls and substantially oriented in a uniform direction. In some embodiments this directional force is applied by rolling a cylindrical element over the fabric layer. In other embodiments this directional force is applied by passing a rubbing material over the surface of a nanotube fabric layer. In other embodiments this directional force is applied by running a polishing material over the nanotube fabric layer for a predetermined time. Exemplary rolling, rubbing, and polishing apparatuses are also disclosed.

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Abstract: Methods for passivating a nanotube fabric layer within a nanotube switching device to prevent or otherwise limit the encroachment of an adjacent material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous nanotube fabric layer to fill in the voids within the porous nanotube fabric layer while one or more other material layers are applied adjacent to the nanotube fabric layer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the nanotube fabric layer) is used to form a barrier layer within a nanotube fabric layer. In other embodiments, individual nanotube elements are combined with and nanoscopic particles to limit the porosity of a nanotube fabric layer.

Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.

Abstract: Methods for passivating a nanotube fabric layer within a nanotube switching device to prevent or otherwise limit the encroachment of an adjacent material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous nanotube fabric layer to fill in the voids within the porous nanotube fabric layer while one or more other material layers are applied adjacent to the nanotube fabric layer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the nanotube fabric layer) is used to form a barrier layer within a nanotube fabric layer. In other embodiments, individual nanotube elements are combined with and nanoscopic particles to limit the porosity of a nanotube fabric layer.

Abstract: The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.

Abstract: The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.

Abstract: The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. A photoresist layer is patterned to simultaneously define mask elements in the array, interface and periphery areas. The pattern is transferred to an amorphous carbon layer. Spacers are formed on the sidewalls of the patterned amorphous carbon layer. Protective material is deposited and patterned to expose mask elements in the array region and in parts of the interface or periphery areas. Exposed amorphous carbon is removed, leaving free-standing spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which the substrate is etched.

Abstract: Methods for passivating a nanotube fabric layer within a nanotube switching device to prevent or otherwise limit the encroachment of an adjacent material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous nanotube fabric layer to fill in the voids within the porous nanotube fabric layer while one or more other material layers are applied adjacent to the nanotube fabric layer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the nanotube fabric layer) is used to form a barrier layer within a nanotube fabric layer. In other embodiments, individual nanotube elements are combined with and nanoscopic particles to limit the porosity of a nanotube fabric layer.

Abstract: Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.

Abstract: Methods for passivating a carbonic nanolayer (that is, material layers comprised of low dimensional carbon structures with delocalized electrons such as carbon nanotubes and nanoscopic graphene flecks) to prevent or otherwise limit the encroachment of another material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous carbonic nanolayer to fill in the voids within the porous carbonic nanolayer while one or more other material layers are applied over or alongside the carbonic nanolayer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the carbonic nanolayer) is used to form a barrier layer within a carbonic nanolayer. In other embodiments, carbon structures are combined with and nanoscopic particles to limit the porosity of a carbonic nanolayer.

Abstract: A process may include forming a mask directly on and above a region selected as an initial semiconductor fin on a substrate and reducing the initial semiconductor fin forming a semiconductor fin that is laterally thinned from the initial semiconductor fin. The process may be carried out causing the mask to recede to a greater degree in the lateral direction than the vertical direction. In various embodiments, the process may include removing material from the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded mask. Electronic devices may include the thinned semiconductor fin as part of a semiconductor device.

Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Abstract: An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening having a lateral cavity therein, the vertical opening extending below the lateral cavity. The lateral cavity may include faceted sidewalls.

Abstract: Methods for passivating a carbonic nanolayer (that is, material layers comprised of low dimensional carbon structures with delocalized electrons such as carbon nanotubes and nanoscopic graphene flecks) to prevent or otherwise limit the encroachment of another material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous carbonic nanolayer to fill in the voids within the porous carbonic nanolayer while one or more other material layers are applied over or alongside the carbonic nanolayer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the carbonic nanolayer) is used to form a barrier layer within a carbonic nanolayer. In other embodiments, carbon structures are combined with and nanoscopic particles to limit the porosity of a carbonic nanolayer.

Abstract: NRAM arrays with nanotube blocks, traces and planes, and methods of making the same are disclosed. In some embodiments, a nanotube memory array includes a nanotube fabric layer disposed in electrical communication with first and second conductor layers. A memory operation circuit including a circuit for generating and applying a select signal on first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers is provided. At least two adjacent memory cells are formed in at least two selected cross sections of the nanotube fabric and conductor layers such that each memory cell is uniquely addressable and programmable. For each cell, a change in resistance corresponds to a change in an informational state of the memory cell. Some embodiments include bit lines, word lines, and reference lines. In some embodiments, 6F2 memory cell density is achieved.

Abstract: Methods for passivating a carbonic nanolayer (that is, material layers comprised of low dimensional carbon structures with delocalized electrons such as carbon nanotubes and nano-scopic graphene flecks) to prevent or otherwise limit the encroachment of another material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous carbonic nanolayer to fill in the voids within the porous carbonic nanolayer while one or more other material layers are applied over or alongside the carbonic nanolayer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the carbonic nanolayer) is used to form a barrier layer within a carbonic nanolayer. In other embodiments, carbon structures are combined with and nanoscopic particles to limit the porosity of a carbonic nanolayer.

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. A photoresist layer is patterned to simultaneously define mask elements in the array, interface and periphery areas. The pattern is transferred to an amorphous carbon layer. Spacers are formed on the sidewalls of the patterned amorphous carbon layer. Protective material is deposited and patterned to expose mask elements in the array region and in parts of the interface or periphery areas. Exposed amorphous carbon is removed, leaving free-standing spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which the substrate is etched.