Abstract: A digital-to-analog converter (10) performs two distinct conversions (12,59) of most significant bits (MSBs) and least significant bits (LSBs), respectively, of a digital input signal and uses the conversion results to provide an equivalent analog output. A plurality of current sources (34-36) is controlled by a thermometer code equivalent value of the most significant bits to provide a first input current to an output stage (22). A plurality of resistors (60-63) is controlled by a binary to `one of` equivalent of the least significant bits to provide a second input current to the output stage. The output stage (22) converts a combination of the first and second input currents to the analog output.

Abstract: A digital encoder (34) is partitioned into a plurality of rank ordered encoder circuits (36-39) which concurrently encodes least significant bits of an input signal from a first digital format to an output signal in a second digital format. Simultaneously, at least one bit of the input signal is used by a most significant bit encoder (42) to provide at least one most significant bit of the input signal in the second digital format. The at least one most significant bit is also used to select an output encoding of one of the plurality of rank ordered encoder circuits (36-39)as a remainder of the bits of the output signal in the second digital format.

Abstract: A circuit (10) and method for minimizing nonlinearity errors in an oversampled data converter (40) resulting from errors in the intended values of components (42-49) of the converter (40). An adder section (11) is used to add a digital input sample to a previously existing sum generated from an immediately preceding digital input sample. A resulting sum is converter from binary code to thermometer code by an encoder (20). Combinatorial logic (24) is used to provide control signals for controlling switching of the components in a manner which both converts the nonlinearity error to a noise error and frequency shifts the noise error out of a frequency passband of the converter to higher frequencies where the error is subsequently filtered.

Abstract: A fully-differential relaxation-type voltage controlled oscillator (VCO) (30) includes an operational transconductance amplifier (OTA) (31) for receiving a differential input voltage. The OTA (31) provides a charging current to a capacitor (33) proportional to the differential input voltage during a first phase of an output signal, and provides a discharging current to the capacitor (33) proportional to the differential input voltage during a secon d phase of the output signal. A comparator having hysteresis (34) detects the charge on the capacitor. A latching portion (35) latches the output of the comparator (34) to provide non-overlapping clock signals.

Abstract: A tuning circuit (30) provides selection signals to a passive component array (80) in a continuous-time filter (70) to compensate for wide variations in values which are encountered in integrated circuit processing. The tuning circuit (30) includes at least one capacitor (46) and at least one resistor (31), and a plurality of either capacitors or resistors. A largest component is enabled and an integration of a reference current during a predetermined period is performed. If the integration provides a voltage greater than a reference voltage, then a corresponding selection signal is set and the component is selected. Successive integrations are performed to determine which components are enabled by corresponding selection signals in order to enable a combination of components which most closely integrates the reference current to the reference voltage. When selection signals corresponding to all components have been determined, the selection signals are applied to corresponding components in the filter (70).