Abstract: Provided is a method for manufacturing an all-solid-state battery which allows a solid electrolyte layer and an electrode to be in sufficiently close in contact with each other without deformation of the electrode shape or damages upon the electrode. The method for manufacturing an all-solid-state battery includes applying slurry for a solid electrolyte layer to the surface of an electrode active material layer to form a patterned solid electrolyte layer, and carrying out pressurization to form a solid electrolyte layer.

Abstract: A memory device includes a memory cell array and an input/output circuit. The input/output circuit is configured to: (i) generate second data in response to sampling first data by comparing the first data against a reference voltage, (ii) generate an offset calibration code corresponding to a first input offset of the input/output circuit based on the second data, prior to receiving a mode register code, (iii) change a gain of an input buffer corresponding to the mode register code after receiving the mode register code, and (iv) calibrate a second input offset corresponding to the changed gain of the input buffer by adjusting a current amount applied to a current element electrically connected to an input terminal of the input buffer based on the offset calibration code and the mode register code. Control logic may also be used to provide the mode register code, which includes gain information associated with the input/output circuit, to the input/output circuit.

Abstract: Disclosed is a memory device, which comprises a memory cell array that includes a plurality of memory cells; an input/output circuit configured to transmit data received from an outside (e.g., an external source) through a data pad to the memory cell array or transmit data read from the memory cell array to the external source; and an impedance calibration circuit configured to generate an impedance calibration code that is applied to the input/output circuit. The impedance calibration circuit is further configured to divide a total impedance calibration section into a plurality of sub-impedance calibration sections, and perform at least one sub-impedance calibration in each of the plurality of sub-impedance calibration sections, the at least one sub-impedance calibration corresponding to at least one of a plurality of impedance modes.

Abstract: A multilayer electronic component according to an example embodiment of the present disclosure includes: a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer; and an external electrode disposed on the body, wherein the external electrode includes an electrode layer disposed on the body and connected to an internal electrode and including Cu and glass, and a plating layer disposed on the electrode layer, at least a portion of the Cu and at least a portion of the glass are disposed adjacent to the plating layer, and an oxide including Cu is disposed on at least a portion of Cu and at least a portion of the glass disposed adjacent to the plating layer.

Abstract: A capacitor component may include: first and second connection conductive layers; a plurality of conductive nanowires respectively connecting the first and second connection conductive layers; a conductive body disposed between the first and second connection conductive layers to have a plurality of through-holes in which the plurality of conductive nanowires are disposed; and a dielectric film disposed so that at least a portion thereof is disposed between the plurality of conductive nanowires and the conductive body in the plurality of through-holes, wherein an aspect ratio, which is a ratio of a length to a width of one of the plurality of conductive nanowires, may be 1000 or more.

Abstract: A multilayer electronic component includes a body including a dielectric layer and internal electrodes; and external electrodes disposed on the body, wherein the dielectric layer includes a plurality of dielectric grains having a perovskite-based composition represented by ABO3, the A includes a first element including at least one of Bi, Na, K, Sr, and Ca, and the B includes a second element including Ti, wherein at least one of the plurality of dielectric grains has a core-shell structure, and a content of the first element included in the core portion is twice or more than a content of the first element included in the shell portion, and wherein the core portion includes a first core portion on an internal side and a second core portion covering at least a portion of the first core portion, and the second core portion includes Zr.

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

Abstract: An error-proof operating system for a portable gas hob includes a gas tank cavity partition having two ends respectively fixed to a front panel and a back panel, wherein a bounce limiting device is provided on the gas tank cavity partition, the bounce limiting device is connected to an actuating rod, the actuating rod is rotatably connected to the gas tank cavity partition, one end of the actuating rod penetrates through the front panel, and a top of the bounce limiting device is not lower than a bearing end for bearing a liquid holding tray. The beneficial effect of the present invention is: by providing the bounce limiting device and using same in conjunction with the liquid holding tray, user's operation is standardized to avoid dangerous accidents caused by incorrect operating.

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

Abstract: A manufacturing method of a dielectric ceramic composition includes attaching a reactive functional group to a surface of a base material powder particle of a perovskite structure.

Abstract: A method of producing a core-shell particle includes introducing a barium titanate-based base powder and an additive to a reactor, and exposing the barium titanate-based base powder and the additive to a thermal plasma torch to obtain core-shell particles including a core portion having barium titanate (BaTiO3) and a shell portion including the additive and formed on a surface of the core portion.

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

Abstract: A dielectric composition includes a ceramic powder, a high polymerization binder, and a low polymerization binder type dispersant having a degree of polymerization between 100 and 1,000.

Abstract: A method of producing a core-shell particle includes introducing a barium titanate-based base powder and an additive to a reactor, and exposing the barium titanate-based base powder and the additive to a thermal plasma torch to obtain core-shell particles including a core portion having barium titanate (BaTiO3) and a shell portion including the additive and formed on a surface of the core portion.

Abstract: A capacitor component includes a body including a plurality of dielectric layers and first and second internal electrodes, alternately disposed to face each other with respective dielectric layers interposed therebetween, and first and second external electrodes disposed on external surfaces of the body and connected to the first and second internal electrodes, respectively. The body includes a capacitance forming portion, in which capacitance is formed by including the first and second internal electrodes, cover portions disposed above and below the capacitance forming portion, respectively, and margin portions disposed on both side surfaces of the capacitance forming portion, respectively. At least one selected from the cover portions and the margin portions includes a plurality of graphene platelets.

Abstract: By controlling shapes of internal electrodes, when short-circuit occurs between the internal electrodes, a short-circuited portion may be opened by an overcurrent, to serve as a fuse. Also, by controlling shapes of internal electrodes, equivalent series inductance (ESL) at a high frequency may be reduced.

Abstract: A method of manufacturing a multilayer ceramic capacitor includes forming a water-repellent coating layer on surfaces of a multilayer ceramic capacitor having an internal electrode, a dielectric layer, and an external electrode; and removing at least a portion of the water-repellent coating layer formed on the surfaces of the external electrode such that another portion of the water-repellent coating layer remains on surfaces of the dielectric layer. The external electrode has first and second surfaces opposing each other in a thickness direction, third and fourth surfaces opposing each other in a width direction, and fifth and sixth surfaces opposing each other in a length direction.

Abstract: Disclosed is an image processing apparatus and method for generating one HDR image by using a plurality of LDR images photographed at different exposure values. The image processing apparatus may include a deep learning framework configured to receive a plurality of low dynamic range (LDR) images captured at different exposures, generate kernels for alignment by using the plurality of LDR images, generate aligned images by applying the kernels to the plurality of LDR images, and generate a high dynamic range (HDR) image by synthesizing the aligned images.

Abstract: Provided is a method for manufacturing an all-solid-state battery which allows a solid electrolyte layer and an electrode to be in sufficiently close in contact with each other without deformation of the electrode shape or damages upon the electrode. The method for manufacturing an all-solid-state battery includes applying slurry for a solid electrolyte layer to the surface of an electrode active material layer to form a patterned solid electrolyte layer, and carrying out pressurization to form a solid electrolyte layer.