Abstract: An apparatus for detecting an angle of rotation includes a rotatable member situated in a first plane and rotatable to be switched between a reference state and rotated states, the rotatable member being unrotated in the reference state, magnet pieces arranged on the rotatable member along a circumferential direction of the rotatable member at intervals of an angle, the magnet pieces moving along a first locus as the rotatable member is rotated, a Hall sensor lying in a second plane spaced a distance apart from the first plane and positioned along a second locus, said second locus being a projection of the first locus into the second plane, and the Hall sensor providing an output varying as the rotatable member is rotated, and a processor configured to detect an angle of rotation of the rotatable member in response to the output from the Hall sensor.

Abstract: An apparatus for detecting an angle of rotation includes a rotatable member situated in a first plane and rotatable to be switched between a reference state and rotated states, the rotatable member being unrotated in the reference state, magnet pieces arranged on the rotatable member along a circumferential direction of the rotatable member at intervals of an angle, the magnet pieces moving along a first locus as the rotatable member is rotated, a Hall sensor lying in a second plane spaced a distance apart from the first plane and positioned along a second locus, said second locus being a projection of the first locus into the second plane, and the Hall sensor providing an output varying as the rotatable member is rotated, and a processor configured to detect an angle of rotation of the rotatable member in response to the output from the Hall sensor.

Abstract: A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and having a stepwise pattern, wherein the plurality of word lines each have a pad region, and a plurality of contact plugs coupled to the respective pad regions of the word lines, wherein a width of a pad region of a first one of the plurality of word lines is greater than a width of a pad region of a second word line lower than the first word line.

Abstract: A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a first etching process for etching the overlying layer to form an overlying layer pattern; forming a spacer on a sidewall of the overlying layer pattern; and performing a second etching process using plasma including a etch gas and an additive gas, to etch the high-k material layer, wherein an amount of the additive gas is substantially the same as the main etch gas to increase an etch selectivity with respect to the substrate.

Abstract: A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a first etching process for etching the overlying layer to form an overlying layer pattern; forming a spacer on a sidewall of the overlying layer pattern; and performing a second etching process using plasma including a etch gas and an additive gas, to etch the high-k material layer, wherein an amount of the additive gas is substantially the same as the main etch gas to increase an etch selectivity with respect to the substrate.

Abstract: A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a first etching process for etching the overlying layer to form an overlying layer pattern; forming a spacer on a sidewall of the overlying layer pattern; and performing a second etching process using plasma including a etch gas and an additive gas, to etch the high-k material layer, wherein an amount of the additive gas is substantially the same as the main etch gas to increase an etch selectivity with respect to the substrate.

Abstract: A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a first etching process for etching the overlying layer to form an overlying layer pattern; forming a spacer on a sidewall of the overlying layer pattern; and performing a second etching process using plasma including a etch gas and an additive gas, to etch the high-k material layer, wherein an amount of the additive gas is substantially the same as the main etch gas to increase an etch selectivity with respect to the substrate.

Abstract: A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion.

Abstract: A semiconductor device includes a substrate and a plurality of active pillars disposed on the substrate and spaced apart from each other by trenches. Each of the active pillars includes a buried metal silicide pattern and an active region stacked on the buried metal silicide pattern, and the active region includes impurity junction regions.

Abstract: A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion.

Abstract: A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion.

Abstract: A semiconductor device includes a substrate and a plurality of active pillars disposed on the substrate and spaced apart from each other by trenches. Each of the active pillars includes a buried metal silicide pattern and an active region stacked on the buried metal silicide pattern, and the active region includes impurity junction regions.

Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

Abstract: A method for fabricating a semiconductor device includes forming a fuse over a substrate, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, selectively removing the anti-reflective layer, forming an insulation layer over a whole surface of the resultant structure including the fuse, and performing repair-etching such that part of the insulation layer remains above the fuse.

Abstract: A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and having a stepwise pattern, wherein the plurality of word lines each have a pad region, and a plurality of contact plugs coupled to the respective pad regions of the word lines, wherein a width of a pad region of a first one of the plurality of word lines is greater than a width of a pad region of a second word line lower than the first word line.

Abstract: A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion.

Abstract: Disclosed herein is a system for diagnosing a deficient pulse and an forceful pulse. The system includes a pulse diagnotic device, a deficient pulse and forceful pulse determining device, and an output device. The pulse diagnotic device measures pulse condition information at an examinee's Cun (˜\f˜) Gu (H), and Chi (,R) pulse-taking locations on his or her wrist using one or more pulse-taking sensors. The deficient pulse and forceful pulse determining device is operably connected to the pulse diagnotic device, analyzes the pulse pressure information measured by the pulse diagnotic device, calculates a quantified deficiency/forceful coefficient, and determines whether a pulse of interest is a deficient pulse or an forceful pulse. The output device is connected to the determining device and displays results of the determination.

Abstract: A data storage device determines a zone layout based on a quality evaluation factor. The zone layout is designed such that a measurement value of the quality evaluation factor for each track in each zone is within a range between a predetermined upper limit and a predetermined lower limit and a maximum amount of variation of the measurement value within each zone is substantially equal to a difference between the upper limit and the lower limit.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of plugs over a die region and an edge bead removal (EBR) region of a wafer, forming metal lines coupled to the plugs, removing the metal lines in the EBR region, forming an inter-layer dielectric layer over the wafer, and forming a plurality of contact holes that expose the metal lines by selectively etching the inter-layer dielectric layer through a dry etch process using a plasma etch device.