Patents by Inventor Hae-Jung Lee
Hae-Jung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120108073Abstract: A method for fabricating a semiconductor device includes forming a plurality of patterns, forming an etch target layer to gap-fill the plurality of patterns, forming an impurity region in the etch target layer, and performing an etch-back process on the etch target layer using the impurity region as an etch stop barrier.Type: ApplicationFiled: December 30, 2010Publication date: May 3, 2012Inventors: Hae-Jung LEE, Eun-Mi Kim, Kyung-Bo Ko
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Patent number: 8139308Abstract: A method of controlling a flying height of a magnetic head of a hard disk drive includes calculating a corrected flying on demand (FOD) voltage to correct a difference between a measured flying height measured by applying a burn-in FOD voltage corresponding to a target flying height and a burn-in flying height in a reference FOD voltage profile corresponding to the burn-in FOD voltage, using the reference FOD voltage profile, in the reference FOD voltage profile that is a profile of a second signal for calculating the flying height of the magnetic head with respect to a first signal for calculating an FOD voltage that allows an end of the magnetic head to thermally expand and protrude when applied to a heater included in the magnetic head, and applying an applied FOD voltage obtained by applying the corrected FOD voltage, to the burn-in FOD voltage, to control the flying height of the magnetic head.Type: GrantFiled: April 24, 2008Date of Patent: March 20, 2012Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Young-Shin Kim, Hae Jung Lee, Chang-Hwan Lee
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Publication number: 20110266648Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.Type: ApplicationFiled: July 15, 2011Publication date: November 3, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yong-Tae CHO, Hae-Jung LEE, Eun-Mi KIM, Kyeong-Hyo LEE
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Publication number: 20110266634Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.Type: ApplicationFiled: July 15, 2011Publication date: November 3, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yong-Tae CHO, Hae-Jung LEE, Eun-Mi KIM, Kyeong-Hyo LEE
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Publication number: 20110242707Abstract: A hard disk drive includes a magnetic head to write data to a disk by magnetizing the disk using a leakage magnetic flux that leaks in a disk direction through a write gap provided between a write pole to apply a magnetic field to the disk and a shield provided separately from the write pole, and an actuator arm allowing the magnetic head to pivot over the disk. In the hard disk drive, the write gap is asymmetrically formed to a left and a right with respect to a center axis line of the write pole according to a movement direction of the magnetic head when the magnetic head pivots over the disk.Type: ApplicationFiled: April 4, 2011Publication date: October 6, 2011Applicant: Samsung Electronics Co., LtdInventors: Yong-Bae YOON, Hae Jung Lee
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Patent number: 8030205Abstract: A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.Type: GrantFiled: November 13, 2009Date of Patent: October 4, 2011Assignee: Hynix Semiconductor Inc.Inventors: Hae-Jung Lee, Sang-Hoon Cho, Suk-Ki Kim
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Patent number: 8003485Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.Type: GrantFiled: December 30, 2008Date of Patent: August 23, 2011Assignee: Hynix Semiconductor Inc.Inventors: Yong-Tae Cho, Hae-Jung Lee, Eun-Mi Kim, Kyeong-Hyo Lee
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Publication number: 20110159687Abstract: A method for fabricating a semiconductor device includes forming a plurality of plugs over a die region and an edge bead removal (EBR) region of a wafer, forming metal lines coupled to the plugs, removing the metal lines in the EBR region, forming an inter-layer dielectric layer over the wafer, and forming a plurality of contact holes that expose the metal lines by selectively etching the inter-layer dielectric layer through a dry etch process using a plasma etch device.Type: ApplicationFiled: July 9, 2010Publication date: June 30, 2011Inventors: Hae-Jung Lee, Kang-Pok Lee, Kyeong-Hyo Lee
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Patent number: 7957086Abstract: A method of controlling a flying height of a magnetic head of a hard disk drive apparatus includes producing a reference FOD (flying on demand) voltage profile defining a relationship between the flying height of the magnetic head and an FOD voltage at a measured temperature, wherein an end of the magnetic head thermally expands and protrudes when the FOD voltage is applied to a heater included in the magnetic head and setting the reference FOD voltage profile that is corrected using a reference maximum flying height of the magnetic head that is preset at room temperature, as an applied FOD voltage profile to control the flying height of the magnetic head.Type: GrantFiled: February 15, 2008Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hwan Lee, Hae Jung Lee
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Publication number: 20110080820Abstract: A data storage device determines a zone layout based on a quality evaluation factor. The zone layout is designed such that a measurement value of the quality evaluation factor for each track in each zone is within a range between a predetermined upper limit and a predetermined lower limit and a maximum amount of variation of the measurement value within each zone is substantially equal to a difference between the upper limit and the lower limit.Type: ApplicationFiled: September 30, 2010Publication date: April 7, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-chul SHIM, Hae-Jung LEE
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Publication number: 20110047409Abstract: A storage device having an automatic backup function, which is connected to a host apparatus to store user data, is provided. The storage device includes a storage medium which stores the user data, and a controller which controls data writing and reading of the storage medium. The controller backs up at least a portion of the user data stored in the storage medium in an available region of the storage medium when the storage device is in an idle mode.Type: ApplicationFiled: July 27, 2010Publication date: February 24, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Wook HUR, Hae Jung LEE
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Patent number: 7835095Abstract: An apparatus and method of setting up a bit error rate (BER) criterion and an apparatus and method of performing a burn-in test using the method of setting up the BER criterion. The method of setting the BER criterion includes measuring temperatures of hard disc drives (HDDs), and changing a BER criterion in which, if the measured temperature of the HDD is higher than an optimum temperature for a burn-in test, a new BER criterion having a value greater than the BER criterion of the optimum temperature is set up, and, if the measured temperature of the HDD is lower than an optimum temperature for a burn-in test, a new BER criterion having a value less than the BER criterion of the optimum temperature is set up.Type: GrantFiled: March 5, 2008Date of Patent: November 16, 2010Assignee: Samsung Electronics Co. LtdInventors: Sang-hyub Lee, Hae-jung Lee
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Patent number: 7709367Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.Type: GrantFiled: June 12, 2007Date of Patent: May 4, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hae-Jung Lee, Ik-Soo Choi, Chang-Youn Hwang, Mi-Hyune You
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Patent number: 7678676Abstract: A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns.Type: GrantFiled: December 30, 2008Date of Patent: March 16, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Hae-Jung Lee, Jae-Seon Yu, Jae-Kyun Lee, Sang-Rok Oh
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Publication number: 20100062598Abstract: A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.Type: ApplicationFiled: November 13, 2009Publication date: March 11, 2010Inventors: Hae-Jung LEE, Sang-Hoon Cho, Suk-Ki Kim
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Patent number: 7660059Abstract: Provided are a method of improving a recording performance of a hard disk drive (HDD) by controlling write strength according to a flying height of a head and a computer-readable recording medium having recorded thereon a computer-readable program suitable for the method. The method of controlling write strength of the HDD includes calculating the flying height of the head before starting a recording operation and controlling the write strength according to the calculated flying height. Accordingly, optimal writing can be performed by the write strength according to the head flying height.Type: GrantFiled: May 9, 2006Date of Patent: February 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-june Ahn, Hae-jung Lee, Seon-mi Hwang
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Publication number: 20100025806Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.Type: ApplicationFiled: December 30, 2008Publication date: February 4, 2010Applicant: Hynix Semiconductor Inc.Inventors: Yong-Tae Cho, Hae-Jung Lee, Eun-Mi Kim, Kyeong-Hyo Lee
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Publication number: 20100022895Abstract: Disclosed herein is a system for diagnosing a deficient pulse and an forceful pulse. The system includes a pulse diagnotic device, a deficient pulse and forceful pulse determining device, and an output device. The pulse diagnotic device measures pulse condition information at an examinee's Cun (˜\f˜) Gu (H), and Chi (,R) pulse-taking locations on his or her wrist using one or more pulse-taking sensors. The deficient pulse and forceful pulse determining device is operably connected to the pulse diagnotic device, analyzes the pulse pressure information measured by the pulse diagnotic device, calculates a quantified deficiency/forceful coefficient, and determines whether a pulse of interest is a deficient pulse or an forceful pulse. The output device is connected to the determining device and displays results of the determination.Type: ApplicationFiled: September 28, 2007Publication date: January 28, 2010Applicant: KOREA INSTITUTE OF ORIENTAL MEDICINEInventors: Jong Yeol Kim, Jeon Lee, Yu Jung Lee, Si Woo Lee, Jaehwan Kang, Hyunhee Ryu, Hae-Jung Lee, Eun-Ji Choi
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Publication number: 20100015775Abstract: A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns.Type: ApplicationFiled: December 30, 2008Publication date: January 21, 2010Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Hae-Jung Lee, Jae-Seon Yu, Jae-Kyun Lee, Sang-Rok Oh
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Patent number: 7648909Abstract: A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.Type: GrantFiled: December 30, 2005Date of Patent: January 19, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Hae-Jung Lee, Sang-Hoon Cho, Suk-Ki Kim