Abstract: A multilevel processing in memory (PIM) includes a processor in which an optimal operator installed at several layers of memory, an accelerator type circuit for processing an irregular operation, and a scheduler for processing an irregular operation have been installed. The multilevel processing in memory includes a memory module including at least one rank in which a computation operation and a data storage operation are performed in response to a control command from a memory controller. The memory module, the rank, a PIM command scheduler included in the rank, a bank group processing unit, and a bank group constitute a plurality of layers, respectively.

Abstract: A processing-in-memory device includes a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, a sense amplifier circuit coupled to the plurality of bit lines, and a control circuit configured to perform a row data copy operation that copies data of a first word line to a second word line, among the plurality of word lines. The control circuit is configured to sequentially perform operations according to an active control signal, a row close control signal, and a row open control signal to perform the row data copy operation.

Abstract: A processing-in-memory (PIM)-based accelerating device includes a plurality of PIM devices, a PIM network system configured to control traffic of signals and data for the plurality of PIM devices, and a first interface configured to perform interfacing with a host device. The PIM network system controls the traffic so that the plurality of PIM devices perform different operations, the plurality of PIM devices perform different operations in groups, or the plurality of PIM devices perform the same operation in parallel.

Abstract: A memory device includes a plurality of memory circuits, and a filtering circuit. The filtering circuit is configured to perform a filtering operation on data and to transmit filtered data to the plurality of memory circuits or to outside of the memory device.

Abstract: A semiconductor device includes a cell circuit including a plurality of memory arrays, and a control circuit configured to control the cell circuit. A memory array of the plurality of memory arrays has a plurality of sub-arrays including a first sub-array and a second sub array, and an array connecting circuit configured to connect bit lines of the first sub-array to respective corresponding bit lines of the second sub-array according to a copy signal. The semiconductor device may further include a partial sum circuit configured to perform charge sharing between a plurality of bit lines of the first sub-array.

Abstract: The present invention provides a dot film, a multi-layers optic sheet comprising the dot film, and a smart electric board having the multi-layers optic sheet attached thereto, the dot film comprising: a base layer made of a synthetic resin; a resin layer coated with a resin mixture on the rear surface of the base layer; and a dot layer on which fine dots are formed by printing such that a printing material permeates the resin layer, wherein the dot layer has a plurality of dots formed therewith which are spaced apart from each other at crossing points of virtual grid lines, and has location information encrypted therein so as to determine location information of an electronic pen when writing with the electronic pen.

Abstract: A semiconductor device includes a cell circuit including a plurality of memory arrays, and a control circuit configured to control the cell circuit. A memory array of the plurality of memory arrays has a plurality of sub-arrays including a first sub-array and a second sub array, and an array connecting circuit configured to connect bit lines of the first sub-array to respective corresponding bit lines of the second sub-array according to a copy signal. The semiconductor device may further include a partial sum circuit configured to perform charge sharing between a plurality of bit lines of the first sub-array.

Abstract: The present invention provides a dot film, a multi-layers optic sheet comprising the dot film, and a smart electric board having the multi-layers optic sheet attached thereto, the dot film comprising: a base layer made of a synthetic resin; a resin layer coated with a resin mixture on the rear surface of the base layer; and a dot layer on which fine dots are formed by printing such that a printing material permeates the resin layer, wherein the dot layer has a plurality of dots formed therewith which are spaced apart from each other at crossing points of virtual grid lines, and has location information encrypted therein so as to determine location information of an electronic pen when writing with the electronic pen.

Abstract: An address counting circuit includes an address counter suitable for counting an address in response to a counting signal; and a counting control block suitable for controlling the address counter to skip the address of at least one predetermined value.

Abstract: An address counting circuit includes an address counter suitable for counting an address in response to a counting signal; and a counting control block suitable for controlling the address counter to skip the address of at least one predetermined value.

Abstract: A memory system includes a memory device including a plurality of memory cells, and a memory controller suitable for generating a second address based on a first address indicating a defective memory cell, among the plurality of memory cells, and sequentially transmitting the first address and a first command corresponding to the first address, and the second address and a second command corresponding to the second address to the memory device, during write and read operations of the defective memory cell.

Abstract: A memory device includes a plurality of memory cells, a weak address storage block suitable for storing a weak address of a weak cell of which data retention time is shorter than a reference time, among the plurality of memory cells, a refresh counter suitable for generating a counting address, and an address selection block suitable for outputting a refresh address by selecting one of the counting address and the weak address, wherein, in selecting the counting address, the address selection block selects the weak address for a predetermined period, when a value of at least one preset bit of the counting address is changed.

Abstract: A memory system includes a memory device including a plurality of memory cells, and a memory controller suitable for generating a second address based on a first address indicating a defective memory cell, among the plurality of memory cells, and sequentially transmitting the first address and a first command corresponding to the first address, and the second address and a second command corresponding to the second address to the memory device, during write and read operations of the defective memory cell.

Abstract: An address counting circuit includes an address counter suitable for counting an address in response to a counting signal; and a counting control block suitable for controlling the address counter to skip the address of at least one predetermined value.

Abstract: An address counting circuit includes an address counter suitable for counting an address in response to a counting signal; and a counting control block suitable for controlling the address counter to skip the address of at least one predetermined value.

Abstract: A semiconductor device may be provided. The semiconductor device may include a memory area. The memory area may be configured to compare an address with a first failure address and a second failure address to store an input datum into a redundancy area and to output the stored input datum as an output datum or configured to compare the address with the first and failure addresses to correct an error of an input datum stored in a normal area to output the corrected input datum as the output datum. The semiconductor device may include a failure address storage circuit. The failure address storage circuit may be configured to store the address as a first failure address based on a first retention information signal and configured to store the address as a second failure address based on a second retention information signal.

Abstract: A memory device includes a plurality of word lines; a plurality of bit lines; a plurality of memory cells, each memory cell coupled to a corresponding word line among the plurality of word lines and a corresponding bit line among the plurality of bit lines; and a control block suitable for controlling at least two word lines among the plurality of word lines to be activated together, and determining whether or not a weak cell exists, based on a voltage of a bit line corresponding to the activated word lines.

Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Abstract: A memory device may include: a plurality of memory cells; a weak cell information storage unit suitable for storing a weak address and parity information corresponding to one or more weak cells having a shorter data retention time than a reference time, among the plurality of memory cells; an ECC (Error Correction Code) circuit suitable for detecting and correcting an error bit of the one or more weak cells using the parity information; and a refresh control unit suitable for controlling the plurality of memory cells to be refreshed at a cycle equal to or more than the reference time.

Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.