Abstract: Provided are a method and apparatus for multiplexing and demultiplexing variable-length high-speed packets. According to the method and apparatus, a plurality of one-gigabit Ethernet frames are multiplexed into a single 10-gigabit Ethernet frame and the single 10-gigabit Ethernet frame is demultiplexed into the plurality of one-gigabit Ethernet frames. In order to process variable-length high-speed packets, packet multiplexing instead of simple TDM is used and a larger input bandwidth than an output bandwidth is used, so that a statistical multiplex effect is accomplished. In addition, standard interface is used for input and output interface, so existing universal chips can be used.

Abstract: An apparatus for managing Ethernet physical layer registers and a method thereof are provided. The apparatus comprises a central processing unit (CPU) with an external bus interface function, and an interface conversion unit which is connected to the CPU through the external bus interface, converts the external bus interface into management data input/output (MDIO) interface and performs communications with the physical layer apparatus.

Abstract: Provided are a data receiving apparatus that can determine data by adjusting a reference level for determining a logic value of inputted data based on Inter-Symbol Interference in a data signal inputted through a transmission line, and receive the data without errors by compensating for timing margin decrease caused by the inter-symbol interference, and a method thereof. The apparatus includes: a reference generator for monitoring the level of an inputted data signal or generating reference levels according to an external control command; a comparator for comparing the inputted data with the reference levels and determining logic values of the inputted data; a selector for selecting the logic values of the inputted data as a valid logic value; and a selection controller for monitoring the valid logic value of the selector, transmitting a selection control signal to the selector, and controlling a process for selecting the valid logic value.

Abstract: Provided is a topology discovery method for an Ethernet network that can effectively discover a physical topology with respect to the Ethernet network of a mesh structure without developing and using a separate control protocol. The topology discovery method in an Ethernet network includes the steps of: acquiring an interface management information base (MIB) and a bridge MIB; defining and storing information for discovering a physical topology; discovering an edge bridge that divides a boundary between a bridge network and a host network; discovering the physical topology with respect to the bridge network by using the schema; discovering the connection relationship with the host network by using an address learning address forwarding table (AFT) with respect to the edge bridge included in the bridge network; and outputting the connection relationship of the bridge network and the host network as a graph.

Abstract: Provided are a packet processing apparatus for realizing a wire-speed, and a method thereof. The packet processing apparatus realizes a wire-speed by making an inputted packet be processed in another packet processing apparatus instead of processing the inputted packet for itself. The packet processing apparatus for realizing a wire-speed by having an inputted packet processed in a packet processor of another packet processing apparatus by making an inputted packet detour a packet processor into a detour path, includes: a packet classifier for classifying and storing the inputted packet in a multi-queue based on a priority; a queue manager for including the multi-queue, determining a detour packet among packets stored in the multi-queue and marking the packet as a detour packet; and a packet scheduler for transmitting the packet designated as the detour packet to the detour path. The apparatus is used for a packet communication system.

Abstract: Provided is an Ethernet port apparatus supporting multiple physical media, a physical medium managing method, and a switching system using the same. The Ethernet port apparatus of the present research can use and manage multiple transmission media by freely selecting and exchanging the transmission media in a system using an Ethernet port. The Ethernet port apparatus supporting multiple physical media, which includes: a main board unit for supporting hot swap and power supply; a detachable physical medium-based sub-board unit for generating a control signal, transmitting the control signal to the main board means, performing a transceiving function suitable for the desired physical medium; and a physical medium support fixing unit for transmitting variable power, a power control signal, a physical medium control signal, a physical medium state information, and physical medium-dependent bitstream between the main board unit and the sub-board unit.

Abstract: An apparatus and method for a redundancy control in duplex switch boards in a high speed network system are provided. The apparatus includes: a switching unit for switching data inputted one of the duplex switch boards to a destination line card; a state controlling unit for controlling a clock state of an opponent switch board between the duplex switch boards; an IPC controlling unit for controlling an inter processor communication (IPC) of a platform of the communication network system; a processing unit for controlling the IPC controlling unit and the state controlling unit of the duplex switch boards; and a clock controlling unit for synchronizing a clock between the duplex switch boards.

Abstract: Provided is an apparatus for providing a system clock synchronized to a network universally. The apparatus includes a network synchronization reference signal generating unit that outputs a reference signal for network synchronization; a network synchronization controller that generates a first control voltage that allows a first clock pulse to be in synchronization with the reference signal for network synchronization; an OVCXO that generates the first clock pulse by application of the first control voltage; a system synchronization reference signal generator that generates reference signals for system synchronization; a system synchronization controller that generates a second control voltage that allows the system clock to be in synchronization with the reference signal for system synchronization; a VCO that generates a second clock pulse by application of the second control voltage; and a system clock generator that outputs the system clock.

Abstract: Disclosed herein is a 10-gigabit Ethernet line interface apparatus and method of controlling the same. The apparatus has N network processors, a frame multiplexing and demultiplexing block, a 10-gigabit extender sublayer processing block, a 10-gigabit Ethernet physical layer processing block, a 10-gigabit physical layer control logic, a line interface control logic, and a line processor. The N network processors are connected to the switch fabric unit. The frame multiplexing and demultiplexing block provides GMII and XGMII between the N network processors and a 10-gigabit extender sublayer processing block. The present invention can improve transmission speed and packet processing performance of a physical layer to a 10 Gbps level while maintaining basic frame standards of a 1-gigabit Ethernet switch apparatus.

Abstract: An apparatus for managing Ethernet physical layer registers and a method thereof are provided. The apparatus comprises a central processing unit (CPU) with an external bus interface function, and an interface conversion unit which is connected to the CPU through the external bus interface, converts the external bus interface into management data input/output (MDIO) interface and performs communications with the physical layer apparatus.

Abstract: The present invention provides an Ethernet switching apparatus using frame multiplexing and demultiplexing. The Ethernet switching apparatus has a plurality of frame demultiplexers, a plurality of frame multiplexers and a switch fabric chip set. The frame demultiplexers convert at least one 10 gigabits Ethernet frame into a plurality of gigabit Ethernet frames. The frame multiplexers convert a plurality of gigabit Ethernet frames into at least one 10 gigabits Ethernet frame. The switch fabric chip set is provided with input and output interfaces using the GMII, and is connected to the frame demultiplexers and the frame multiplexers in the GMII format. The switch fabric chip set outputs frames through an arbitrary usable one of a plurality of GMII ports connected to a corresponding frame multiplexer if the frames are transmitted to the corresponding frame multiplexer.

Abstract: The present invention presents a method for providing IP multicast service using a virtual LAN, which can provide efficient multicast service in a network by applying the virtual LAN to the IP multicast service. A method for providing IP multicast service using a VLAN in a network including an IP multicast/VLAN manager for supporting an IGMP and a GVRP, and multicast group members, comprising the steps of: after generating an IP multicast group, allowing a sender to request the IP multicast/VLAN manager to search for at least one host joining the IP multicast group; allowing the IP multicast/VLAN manager to check whether the host supports the VLAN; and allowing the sender to transfer a packet through the VLAN if the host joining the IP multicast group supports the VLAN and allowing the sender to broadcast a packet through IP multicast if not.

Abstract: An apparatus, a method and a storage medium for carrying out a deskew among multiple lanes for use in a division transmission of large-capacity data.

Abstract: Provided are a method and apparatus for multiplexing and demultiplexing variable-length high-speed packets. According to the method and apparatus, a plurality of one-gigabit Ethernet frames are multiplexed into a single 10-gigabit Ethernet frame and the single 10-gigabit Ethernet frame is demultiplexed into the plurality of one-gigabit Ethernet frames. In order to process variable-length high-speed packets, packet multiplexing instead of simple TDM is used and a larger input bandwidth than an output bandwidth is used, so that a statistical multiplex effect is accomplished. In addition, standard interface is used for input and output interface, so existing universal chips can be used.

Abstract: Disclosed is a mascara brush for making up eyelashes, especially suitable for the Orientals whose eyelashes are shorter and downwardly curved. The mascara brush according to the present invention includes a spirally twisted wire core at the center thereof; and a plurality of bristles, each being fitted into the wire core at one end thereof and being outwardly extended at the other end. The bristles are 5 mils to 6 mils thick and distributed at the wire core to be installed in 30 to 40 numbers per turn of the spirally twisted wire core. A section through the mascara brush is of a triangular shape. Ridges of 1.7 mm to 2 mm wide are formed at vertexes of the triangular section. A distance A from a bottom to each ridge of the triangular section through the mascara brush is in the range of 5.5 mm to 6 mm.

Abstract: Disclosed is a mascara brush for making up eyelashes, especially suitable for the Orientals whose eyelashes are shorter and downwardly curved. The mascara brush according to the present invention includes a spirally twisted wire core at the center thereof; and a plurality of bristles, each being fitted into the wire core at one end thereof and being outwardly extended at the other end. The bristles are 5 mils to 6 mils thick and distributed at the wire core to be installed in 30 to 40 numbers per turn of the spirally twisted wire core. A section through the mascara brush is of a triangular shape. Ridges of 1.7 mm to 2 mm wide are formed at vertexes of the triangular section. A distance A from a bottom to each ridge of the triangular section through the mascara brush is in the range of 5.5 mm to 6 mm.

Abstract: A coding method for converting m-bit input data into n-bit codeword satisfying DC-free and minimum bandwidth characteristics that includes the following: Select the number of input bits m and the number of output bits n for an (m,n) block code. Accumulate a sufficient number of BUDA (binary unit DSV and ASV) cells to form a BUDA stack for derivation of the state diagram. Pick one node as a state, and secure at least 2{circumflex over ( )}m exit paths of an n-hop length, and denote each terminating node of each path as another state. Start with a new state and repeat the previous step. If the stack needs to be expanded to complete the state diagram, add more cells to the stack either horizontally or vertically as appropriate. Reduce the number of states as possible with all transition paths terminating on one of the arranged states. At each state, arrange the mapping table as an input m-bit combination to an output n-bit combination.