Abstract: A display device with less horizontal crosstalk includes an array of pixel electrodes connected to and driven by a plurality of switching devices, the plurality of pixel electrodes arranged in a matrix, a plurality of gate lines which extend in a row-wise direction and are located between each of the plurality of rows of the pixel electrode array and at both sides of the pixel electrode array, and a plurality of data lines which extend in a column-wise direction and are located between each of the plurality of columns, wherein switching devices of horizontally neighboring pixel electrodes belonging to a given row among the plurality of rows of the pixel electrode array are controlled by gate lines belonging to different rows that are adjacent to the neighboring pixel electrodes.

Abstract: In a liquid crystal display, a liquid crystal panel includes a plurality of pixels. Each of the pixels has a plurality of subpixels corresponding to a red, a green and a blue and is arranged along data lines. The subpixels are formed in pixel regions, which are defined by the data lines and gate lines. First groups of the subpixels are connected to an adjacent left data line and second groups of the subpixels are connected to an adjacent right data line. The data lines are driven by a column inversion driving method such that image data applied to the adjacent data lines have different polarities. Thus, the screen-defects are reduced when the liquid crystal panel is driven by the dot inversion method.

Abstract: A flat panel display with reduced malfunction rate and improved image quality and a method for making such flat panel display are presented. The flat panel display is operated by a gate drive circuit that receives a first gate signal for driving a first gate line at one end of a data line and a second gate signal for driving a second gate line at the other end of the data line. First and second clock signals are supplied to the gate drive circuit, and the width of the first and second clock signal lines are adjusted such that a phase difference between the first gate signal and the second gate signal corresponds to a signal delay time between the two ends of the data line. The first and second clock signal lines and the gate and data lines are integrated.

Abstract: A driving apparatus of a display device including a plurality of switching elements and a plurality of pixel electrodes connected to the switching elements is provided, in which the apparatus includes a gate-off voltage generator for generating a gate-off voltage and a gate driver for outputting the gate-off voltage from the gate-off voltage generator to the switching elements, wherein the gate-off voltage generator increases the gate-off voltage to a predetermined voltage when a power supply voltage applied to the display device is cut off.

Abstract: Disclosed is a liquid crystal display (LCD). An LCD panel is divided into upper and lower panels, and a scanning direction of gate lines of the upper panel is opposite to that of gate lines of the lower panel. The upper panel includes an upper gate line block having a first gate line formed in the horizontal direction and transmits scanning signals, and upper data lines that cross the first gate line and transmit image signals. And the lower panel includes a lower gate line block having a second gate line, and lower data lines that cross the second gate line and are separated from the upper data lines. Upper and lower gate drivers that provide scanning signals to the gate lines of the upper and lower gate line blocks are located on the sides of the upper and lower panels, respectively. The upper and lower gate drivers supply the scanning signals to the gate lines in sequentially opposite directions.

Abstract: Disclosed is a gate signal delay compensating LCD that comprises an LCD panel including a plurality of gate lines, a plurality of data lines insulated from and crossing the gate lines, a plurality of TFT each of which having a gate electrode connected to the gate line and a source electrode connected to the data line, a pixel electrode connected to a drain electrode of the TFT and a common electrode facing the pixel electrode, liquid crystal filled between the pixel electrode and the common electrode, and a signal delay compensator connected to ends of the gate lines to compensate for the gate signal delay; a gate driver for supplying a gate signal for turning on and off the TFT to the gate line so as to drive the LCD panel; a data driver for supplying a data voltage that represents an image signal to the data line so as to drive the LCD panel; and a signal controller connected to a signal source, the gate driver and the data driver, and processing the image signal provided by the signal source to enable the

Abstract: A display device including a plurality of pixel electrodes arranged in a matrix including rows and columns and a plurality switching elements coupled with the pixel electrodes; a plurality of gate lines coupled with the switching elements and extending in a row direction, at least two gate lines assigned to a row; and a plurality of data lines coupled with the switching elements and extending in a column direction, a data line assigned to at least two columns, wherein each of the pixel electrodes has a first side and a second side that is farther from a data line than the first side, and the switching elements are disposed near the second sides of the pixel electrodes.

Abstract: A display device that employs fewer IC chips and lends itself to cost-efficient manufacturing is presented. The device includes: a plurality of pixel rows including first and second pixels alternately arranged; a plurality of first and second gate lines disposed above and below the pixel rows and applying first and second gate-on voltages to the first and the second pixels, respectively; data lines intersecting the first and the second gate lines, each data line disposed between the first and the second pixels in a pair of first and second pixels and applying data voltages to the first and the second pixels; first and second gate drivers applying the first and the second gate-on voltages to the first and the second gate lines; and a data driver applying the data voltages to the data lines, wherein the second gate-on voltage is applied earlier than the first gate-on voltages by a predetermined time.

Abstract: A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.

Abstract: A transistor includes a control electrode, a first current electrode and a second current electrode. The control electrode includes a body portion, and first and second hand portions protruded from first and second ends of the body portion, respectively. The first current electrode is electrically insulated from the control electrode and disposed over a region between the first and second hand portions of the control electrode. A portion of the first current electrode is overlapped with a portion of the control electrode. The second current electrode is electrically insulated from the control electrode and partially overlapped with the body portion, the first hand portion and the second hand portion of the control electrode. Therefore, parasitic capacitance is reduced.

Abstract: Gate-driving circuitry of a thin film transistor array panel is formed on the same plane as a display area of the transistor array panel. The gate-driving circuitry includes driving circuitry and signal lines having apertures. Thus, a sufficient amount of light, even though illuminated from the thin film transistor array panel side, can reach a photosetting sealant overlapping at least in part the gate-driving circuitry. The thin film transistor array panel and the counter panel are put together air-tight and moisture-tight. Consequently, the gate-driving circuitry can avoid corrosion by moisture introduced from outside. Gate-driving circuitry malfunctions can also be reduced.

Abstract: A display device includes pixels, each including a switching element; a shift register comprising stages coupled with the switching elements and sequentially generating output signals; clock signal lines transmitting clock signals; at least a control signal line transmitting a control signal; and terminal lines connecting the clock signal lines and the control signal with the stages, wherein the terminal lines comprise at least one common terminal line commonly connected with at least two stages.

Abstract: An LCD device includes a timing control circuit having a flicker reducing portion for detecting flickers in the entire one frame to be displayed in a liquid crystal panel and controlling a brightness of the backlight according to an amount of detected flickers. The timing control circuit can evidently reduce visually recognized flickers by dimming the brightness of the backlight when the detected flickers is more than given rate.

Abstract: Disclosed is an LCD capable of reducing a size and cost thereof. The LCD module includes an user connecting part (100) that receives power voltages, image signals and control signals from an external host system and outputs the power voltages, image and control signals through a first integrated type connector (102) and an LCD module having a second integrated type connector (310) connected with the first integrated type connector (102) through an FPC. The LCD module receives power voltages and image and control signals through the second integrated type connector (310), provides image data signals and timing signals to data lines and provides scan signals to gate lines. Namely, the LCD can receive power voltage, the image signals and control signals through the integrated type connector (102, 310) instead of a plurality of connecting terminals, thereby providing the LCD having slim weight and compact size and reducing the size thereof.

Abstract: A display device including a plurality of pixels is provided, which includes: a signal controller for processing image data for the pixels from an external source; a plurality of pad areas, each pad area provided with a plurality of conductors for transmission of the image data, the conductors of adjacent two of the pad areas having a correspondence; and a plurality of interconnections connecting the corresponding conductors, wherein each conductor in each pad area transmits one of bits of the image data and the corresponding conductors are arranged in reversed order on the respective pad areas. The display device further includes a plurality of data driver units connected to the respective pad areas and sequentially activated to receive respective image data from the pad areas under control of the signal controller, the data driver units converting the received image data into analog voltages and provides the analog voltage for the pixels under control of the signal controller.

Abstract: Disclosed is a gate signal delay compensating LCD that comprises an LCD panel including a plurality of gate lines, a plurality of data lines insulated from and crossing the gate lines, a plurality of TFT each of which having a gate electrode connected to the gate line and a source electrode connected to the data line, a pixel electrode connected to a drain electrode of the TFT and a common electrode facing the pixel electrode, liquid crystal filled between the pixel electrode and the common electrode, and a signal delay compensator connected to ends of the gate lines to compensate for the gate signal delay; a gate driver for supplying a gate signal for turning on and off the TFT to the gate line so as to drive the LCD panel; a data driver for supplying a data voltage that represents an image signal to the data line so as to drive the LCD panel; and a signal controller connected to a signal source, the gate driver and the data driver, and processing the image signal provided by the signal source to enable the

Abstract: An LCD device includes a timing control circuit having a flicker reducing portion for detecting flickers in the entire one frame to be displayed in a liquid crystal panel and controlling a brightness of the backlight according to an amount of detected flickers. The timing control circuit can evidently reduce visually recognized flickers by dimming the brightness of the backlight when the detected flickers is more than given rate.