Abstract: A control circuit for an isolated power supply is disclosed, the control circuit includes a secondary-side drive signal generator, a secondary-side transistor switch turn-off detector and a primary-side control signal generator. The primary-side control signal generator is configured to: determine a second turn-on instant referring to an turn-off instant of the secondary-side synchronous rectification transistor from the turn-off acknowledgement signal; determine a first turn-on instant referring to a supposed turn-on instant for the primary-side transistor switch from the feedback signal of the output voltage of the isolated power supply; and determine the turn-on instant for the primary-side transistor switch from the second turn-on instant or the first turn-on instant whichever is later, and responsively generate the primary-side transistor switch control signal.

Abstract: A downhole throttling device based on wireless control includes an inlet nozzle, a throttling assembly, an electrical sealing cylinder, a gas guide cylinder, a lower adapter sleeve, an end socket, a female sleeve, and electrical components. The inlet nozzle is connected to the throttling assembly, the throttling assembly is connected to the electrical sealing cylinder and the gas guide cylinder, the electrical sealing cylinder and the gas guide cylinder are both connected to the lower adapter sleeve, the lower adapter sleeve is respectively connected to the end socket and the female sleeve, and the electrical components are arranged in the electrical sealing cylinder. A throttling effect is achieved by detecting the temperature and pressure in a tube by a temperature/pressure sensor in the electrical components and controlling a motor to rotate a movable valve in the throttling assembly by a circuit control assembly, thereby achieving wireless control over downhole throttling.

Abstract: Isolated power supply control circuits, isolated power supply and control method thereof are disclosed, the control circuit for controlling an isolated power supply includes a secondary-side control signal generator and a primary-side control signal generator. The secondary-side control signal generator produces a secondary-side transistor switch control signal containing information about a turn-off instant of a secondary-side synchronous rectification transistor, which serves as a second turn-on instant. The primary-side control signal generator derives, from a feedback signal, a supposed turn-on instant for a primary-side transistor switch, which serves as a first turn-on instant. The primary side turn-on signal generator further derives a turn-on instant for the primary-side transistor switch from the second or first turn-on instant whichever is later and responsively generates a primary-side transistor switch control signal.

Abstract: The present disclosure relates to a processor and a computing system. A processor is provided, including: a pipeline stage, including sequential device(s); and a first clock driving circuit, configured to provide a clock signal to the pipeline stage, wherein the first clock driving circuit includes: a plurality of first clock paths, configured to provide corresponding clock signals respectively; a first selector, configured to select a clock signal from the clock signals provided by the plurality of first clock paths for the pipeline stage.

Abstract: A semiconductor device is disclosed herein. The semiconductor device includes a silicon carbide substrate, trench structures, mesa structures, a first oxide layer, a conductive layer, a second oxide layer, a dielectric layer, and an insulation layer. The trench structures are formed on a surface of the silicon carbide substrate. Each trench structure has sidewalls and a bottom, and each respective mesa structure is formed between the respective adjacent trench structures. The first oxide layer is formed on the sidewalls of the trench structures. The conductive layer is formed on the bottom of the trench structures and on a top surface of each mesa structure. The second oxide layer is formed on the first oxide layer and the conductive layer. The dielectric layer is formed on the second oxide layer. The insulation layer is formed on the dielectric layer.

Abstract: A method for predicting a day-ahead wind power of wind farms, comprising: constructing a raw data set based on a correlation between the to-be-predicted daily wind power, the numerical weather forecast meteorological feature and a historical daily wind power; obtaining a clustered data set and performing k-means clustering, obtaining a raw data set with cluster labels, and generating massive labeled scenes based on robust auxiliary classifier generative adversarial networks; determining the cluster label category of the to-be-predicted day based on the known historical daily wind power and numerical weather forecast meteorological feature, and screening out multiple scenes with high similarity to the to-be-predicted daily wind power based on the cluster label category; and obtaining the prediction results of the to-be-predicted daily wind power at a plurality of set times based on an average value, an upper limit value and a lower limit value of the to-be-predicted daily wind power.

Abstract: A manufacturing process of a DMOS device in a drift region in a semiconductor substrate, having: forming a polysilicon layer above the drift region; forming a block layer above the polysilicon layer; etching both the block layer and the polysilicon layer, through a window of a first masking layer to expose a window to the drift region; implanting dopants through the window to the drift region to form a body region; forming blocking spacers to wrap side walls of the polysilicon layer; implanting dopants into the body region under a window shaped by the blocking spacers to form a body pickup region; etching away the blocking spacers; performing a masking step to form gates; forming ONO spacers to wrap side walls of the gates; and performing a masking step to form source regions and drain pickup regions.

Abstract: The present disclosure discloses a lateral transistor having a source region, a drain region, a gate near the source region side and a field dielectric positioned in or atop a portion of a well region between the drain region and the gate. The lateral transistor further includes a non-conductive field plate positioning layer positioned atop a portion of the field dielectric and separated laterally from the gate with a first lateral distance, a lateral conductive field plate positioned atop the non-conductive field plate positioning layer and separated laterally from the gate with a second lateral distance and a vertical trenched field plate contact extending vertically from a top surface of an interlayer dielectric layer through the interlayer dielectric layer to reach and contact with the lateral conductive field plate.

Abstract: A method of managing files by a mobile device includes generating virtual directory information corresponding to files stored in the mobile device; and transmitting the generated virtual directory information to an external device. In response to the virtual directory information being received by the external device, a virtual directory included in the virtual directory information is displayed on the external device, and the files stored in the mobile device are accessible through the displayed virtual directory.

Abstract: A power conversion system, a controller for the same, and a method for controlling the same. The power conversion system includes a shutdown array and a power converter. The shutdown array includes multiple shutdown strings that are connected in parallel. Each of the multiple shutdown strings includes multiple shutdown devices, where outputs of the multiple shutdown devices are connected in series. An output terminal of the shutdown array is connected to an input terminal of the power converter. An input terminal of each of the multiple shutdown devices is connected to at least one direct-current power supply. The controller sends a shutdown instruction to each shutdown device of the shutdown array in response to receiving a rapid-shutdown command, controls the power converter to discharge an input capacitor of the power converter, and stops discharging the input capacitor in response to an input voltage of the power converter being reduced to a preset voltage.

Abstract: A power conversion system, a controller for the same, and a method for controlling the same. The power conversion system includes a shutdown array and a power converter. The shutdown array includes multiple shutdown strings that are connected in parallel. Each of the multiple shutdown strings includes multiple shutdown devices, where outputs of the multiple shutdown devices are connected in series. An output terminal of the shutdown array is connected to an input terminal of the power converter. An input terminal of each of the multiple shutdown devices is connected to at least one direct-current power supply. The controller sends a shutdown instruction to each shutdown device of the shutdown array in response to receiving a rapid-shutdown command, controls the power converter to discharge an input capacitor of the power converter, and stops discharging the input capacitor in response to an input voltage of the power converter being reduced to a preset voltage.

Abstract: A traditional Chinese medicine immunopotentiator prepared from mulberry leaves polysaccharide and eucommia polysaccharide. The immunopotentiator can stimulate proliferation of chicken lymphocytes in vitro. When used together with newcastle disease vaccine to immunize chickens, the immunopotentiator can increase serum antibody titer, promote proliferation of lymphocytes, and enhance cellular immunity and humoral immunity of the chickens. When used together with porcine productive and respiratory syndrome vaccine to immunize piglets, the immunopotentiator can increase the serum antibody titer. When used together with the porcine productive and respiratory syndrome vaccine to immunize layers, the immunopotentiator can increase porcine productive and respiratory syndrome virus yolk antibody titer and improve immune effects of the vaccine.

Abstract: The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.

Abstract: The present disclosure provides asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuits and signal conversion method thereof. An exemplary ASAR AC circuit includes a sample/hold circuit configured to input a first analog signal and output a second analog signal; a digital-to-analog converter circuit configured to output a third analog signal; a first voltage comparison circuit configured to respond to a valid level of a latch signal, and output a first logic level and a second logic level; a first logic circuit configured to respond to a valid level of a flag signal, and identify a comparison result of the first voltage comparison circuit and output the first digit signal; and a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels independently from the first logic level and the second logic level.

Abstract: The present disclosure provides asynchronous successive approximation register analog-to-digital convener (ASAR ADC) circuits and signal conversion method thereof. An exemplary ASAR AC circuit includes a sample/hold circuit configured to input a first analog signal and output a second analog signal; a digital-to-analog converter circuit configured to output a third analog signal; a first voltage comparison circuit configured to respond to a valid level of a latch signal, and output a first logic level and a second logic level; a first logic circuit configured to respond to a valid level of a flag signal, and identify a comparison result of the first voltage comparison circuit and output the first digit signal; and a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels independently from the first logic level and the second logic level.

Abstract: The present disclosure provides an asynchronous successive approximation register analog-to-digital conversion (ASAR ADC) circuit, including: a comparator circuit, an XOR gate circuit, an ASAR logic circuit, a metastable state detection (MD) circuit, a capacitor, and a digital-to-analog converter (DAC) circuit. The comparator circuit has a first input terminal connected to an analog signal, a first output terminal of the comparator circuit respectively connected to a first input terminal of the ASAR circuit and a first input terminal of the XOR gate circuit, a second output terminal of the comparator circuit respectively connected to a second input terminal of the ASAR gate circuit and a second input terminal of the XOR gate circuit, and an enable signal input terminal connected to a control signal output terminal of the ASAR logic circuit. The XOR gate circuit has an output terminal connected to a third input terminal of the ASAR logic circuit.

Abstract: The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.

Abstract: A traditional Chinese medicine immunopotentiator prepared from mulberry leaves polysaccharide and eucommia polysaccharide. The immunopotentiator can stimulate proliferation of chicken lymphocytes in vitro. When used together with newcastle disease vaccine to immunize chickens, the immunopotentiator can increase serum antibody titer, promote proliferation of lymphocytes, and enhance cellular immunity and humoral immunity of the chickens. When used together with porcine productive and respiratory syndrome vaccine to immunize piglets, the immunopotentiator can increase the serum antibody titer. When used together with the porcine productive and respiratory syndrome vaccine to immunize layers, the immunopotentiator can increase porcine productive and respiratory syndrome virus yolk antibody titer and improve immune effects of the vaccine.

Abstract: Method of forming dual gate insulation layers and semiconductor device having dual gate insulation layers is disclosed. The method of forming dual gate insulation layers comprises forming a first thin layer of a thick gate insulation layer on a semiconductor substrate by oxidizing the semiconductor substrate, depositing a second thicker layer of the thick gate insulation layer on the first thin layer, removing a portion of the thick gate insulation layer to expose a surface area of the semiconductor substrate and forming a thin gate insulation layer on the exposed surface area of the semiconductor substrate. The method of forming dual gate insulation layers, when applied in fabricating semiconductor devices having dual gate insulation layers and trench isolation structures, may help to reduce a silicon stress near edges of the trench isolation structures and reduce/alleviate/prevent the formation of a leaky junction around the edges of the trench isolation structures.