Abstract: A method for preparing a semiconductor device includes: providing a semiconductor substrate, in which a trench is formed on the semiconductor substrate, a filling layer is formed in the trench, and a void is formed in the filling layer; removing a portion of the filling layer to expose the void; forming a plug, in which the plug is configured to plug the void and extends into the void by at least a preset distance; and removing a portion of the filling layer and remaining the plug with at least a preset height until the filling layer reaches a preset thickness to form a contact hole.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.

Abstract: A semiconductor structure manufacturing method includes that a substrate is provided, in which the substrate includes a substrate layer and a plurality of bit line structures arranged on the substrate layer in a first direction, the substrate layer includes shallow trench isolation structures, active areas, and a plurality of word line structures arranged in a second direction, and two adjacent bit line structures and two adjacent word line structures define a conductive contact region, and the conductive contact region exposing part of a corresponding active area; a conducting layer is formed between the bit line structures, the conducting layer covering the substrate layer, and the conducting layer extending along the first direction; part of the conducting layer is removed with the conducting layer corresponding to the conductive contact region retained to form first capacitor wires; and an isolation layer is formed, which fills gaps between the first capacitor wires.

Abstract: Method for forming a capacitor includes following operations. A base is provided. First supporting layer and first sacrificial layer are formed on the base sequentially. First through holes penetrating first supporting layer and first sacrificial layer are formed to expose the base. First through holes are filled to form first filling structures. Second supporting layer covering remaining first sacrificial layer and first filling structures is formed. Second through holes penetrating second supporting layer are formed. Second sacrificial layer covering remaining second supporting layer and second through holes, and third supporting layer are formed. Third through holes penetrating third supporting layer and second sacrificial layer are formed. First filling structures are removed to communicate each of third through holes and corresponding one of first through holes.

Abstract: A semiconductor structure includes a substrate, bit line structures, and capacitor connection lines. A plurality of bit line structures are arranged on the substrate. Contact holes are formed between adjacent bit line structures. A capacitor connection line includes a first conductive block and a second conductive block. The first conductive block and the second conductive block are sequentially filled in a contact hole. A chamfered structure is formed on a top end of the first conductive block. The chamfered structure is adjacent to a bit line structure. A bottom end of the second conductive block matches the chambered structure.

Abstract: Semiconductor structure and manufacturing method thereof are provided. The method includes providing a substrate provided with trenches spaced apart from each other and bit line structures spaced apart from each other, the bit line structures being at least partially located in the trenches; forming a first protection layer at least including a first side wall layer covering a side wall of each of the bit line structures and a second side wall layer covering a surface of each of the trenches; forming a second protection layer fully filling each of the trenches together with the first protection layer and at least including a silicon oxide layer formed by a thermal oxidation method; and forming a third protection layer at least covering a top surface, away from the substrate, of the second protection layer, the second and third protection layers covering a surface of the first side wall layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a base and forming, on the base, a bit line contact region provided with a first groove; forming a first bit line contact layer in the first groove, wherein the first bit line contact layer in the first groove defines a second groove; forming a diffusion layer in the second groove, wherein the diffusion layer in the second groove defines a third groove; forming, in the third groove, a second bit line contact layer provided with a gap; and processing the diffusion layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming active pillars arranged in an array on the substrate, a projection shape of a longitudinal section of each of the active pillars includes a cross shape; forming a first oxide layer on the substrate, where a filling region is formed between adjacent active pillars in the same row; sequentially forming a word line and a dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the active pillars; and forming a capacitor structure on the contact layer.

Abstract: A method for forming a thin film by a deposition process, including: a substrate is placed in a deposition chamber; a precursor is introduced into the deposition chamber to form an adsorption layer on a surface of the substrate; a reactant is introduced into the deposition chamber and reacts with the adsorption layer to form a thin film layer on the surface of the substrate and generate reaction byproducts; a vacuuming operation is performed on the deposition chamber to decrease a chamber pressure therein to reduce desorption energy of the reaction byproducts formed at the surface of the thin film layer; plasma is introduced into the deposition chamber to increase energy of the surface of the formed thin film layer; a cleaning gas is introduced into the deposition chamber to discharge the reaction byproducts and the residual precursor and reactant in the deposition chamber.

Abstract: A preparation method for a semiconductor structure includes the following operations. A bit line structure, active pillars, and a word line structure are formed in turn on a substrate. Bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure. A pillar-shaped conductive structure is formed on the active pillars, and a cup-shaped conductive structure is formed on the pillar-shaped conductive structure. There is an electrode gap between the pillar-shaped conductive structure and the cup-shaped conductive structure, and the pillar-shaped conductive structure and the cup-shaped conductive structure form a lower electrode. A dielectric layer is formed on a surface of the lower electrode. An upper electrode is formed on a surface of the dielectric layer. The upper electrode fills the electrode gap.

Abstract: A semiconductor structure includes a substrate, bit line structures, and capacitor connection lines. A plurality of bit line structures are arranged on the substrate. Contact holes are formed between adjacent bit line structures. A capacitor connection line includes a first conductive block and a second conductive block. The first conductive block and the second conductive block are sequentially filled in a contact hole. A chamfered structure is formed on a top end of the first conductive block. The chamfered structure is adjacent to a bit line structure. A bottom end of the second conductive block matches the chambered structure.

Abstract: The embodiments of the present disclosure belong to the field of semiconductor manufacturing technology and relates to a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing the semiconductor structure includes: a bit line structure is formed on a substrate, a fill channel is formed between the insulating structures on two adjacent bit lines; a conductor is formed within the fill channel; at least one slit is formed on the conductor along a direction perpendicular to a longitudinal direction of each of the plurality of bit line to divide the conductor into a plurality of conductive blocks, each of the plurality of conductive blocks is connected to one of transistors on the substrate.

Abstract: A method for preparing a semiconductor device includes: providing a semiconductor substrate, in which a trench is formed on the semiconductor substrate, a filling layer is formed in the trench, and a void is formed in the filling layer; removing a portion of the filling layer to expose the void; forming a plug, in which the plug is configured to plug the void and extends into the void by at least a preset distance; and removing a portion of the filling layer and remaining the plug with at least a preset height until the filling layer reaches a preset thickness to form a contact hole.

Abstract: Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, and forming bit lines extending in a first direction and trenches between the adjacent bit lines on the substrate; forming a dielectric layer and a contact layer filling the trenches, parts of the dielectric layer and parts of the contact layer being arranged at intervals in the first direction, both the dielectric layer and the contact layer being in contact with the substrate, and the contact layer having first gaps; removing part of the contact layer, to expose the first gaps; forming a filling layer to fill the first gaps; and etching the contact layer and the filling layer back.

Abstract: Provided are a semiconductor structure and a method for preparing the same. The method for preparing a semiconductor structure includes: a substrate is provided; a stacked structure is formed on the substrate; a first capacitor having a first bottom electrode, a first dielectric layer and a first top electrode is formed in the stacked structure, in which the first bottom electrode is of a columnar structure; and a second capacitor having a second bottom electrode, a second dielectric layer and a second top electrode is formed on the first capacitor, in which the second bottom electrode is of a concave structure. The second dielectric layer is formed between the second bottom electrode and the second top electrode, and the second dielectric layer is further formed between the second bottom electrodes of adjacent second capacitors.

Abstract: The present application discloses a semiconductor structure. The semiconductor structure includes: a substrate, the substrate being provided with a conductive structure; a first lower electrode and a second lower electrode sequentially stacked, the first lower electrode being located between the second lower electrode and the substrate, and the first lower electrode being electrically connected to the conductive structure; a first dielectric layer and a first upper electrode, the first dielectric layer covering a sidewall surface of the first lower electrode, and the first upper electrode being located on one side of the first dielectric layer away from the first lower electrode; and a second dielectric layer and a second upper electrode, the second dielectric layer covering an inner wall and a bottom surface of the second lower electrode, and the second upper electrode filling the recess of the second lower electrode.

Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a substrate, bit line structures and isolation walls located on side walls of the bit line structures, and capacitor contact holes. In the substrate, conductive contact regions are arranged. The conductive contact regions are exposed from the substrate. A plurality of discrete bit line structures are located on the substrate. Each of the isolation walls includes at least one isolation layer and a gap between the isolation layer and the bit line structure. Each of the capacitor contact holes is constituted by a region surrounded by the isolation walls between the adjacent bit line structures. The capacitor contact holes expose the conductive contact regions. A top width of the capacitor contact holes is larger than a bottom width thereof in a direction parallel to an arrangement direction of the bit line structures.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method for the semiconductor structure comprises: providing a substrate, wherein the substrate comprises active regions and isolation regions each located between the adjacent active regions, and each of the active regions comprises corner regions adjacent to the isolation regions; performing a doping process to implant doping ions into the corner regions, wherein the doping ions are configured to slow down an oxidation rate of the corner regions; and performing a removing process to remove the oxidized portion of the substrate after the doping process, wherein during the removing process, a side wall of each of the corner regions is exposed from a structure in the isolation region.

Abstract: A semiconductor structure manufacturing method includes that a substrate is provided, in which the substrate includes a substrate layer and a plurality of bit line structures arranged on the substrate layer in a first direction, the substrate layer includes shallow trench isolation structures, active areas, and a plurality of word line structures arranged in a second direction, and two adjacent bit line structures and two adjacent word line structures define a conductive contact region, and the conductive contact region exposing part of a corresponding active area; a conducting layer is formed between the bit line structures, the conducting layer covering the substrate layer, and the conducting layer extending along the first direction; part of the conducting layer is removed with the conducting layer corresponding to the conductive contact region retained to form first capacitor wires; and an isolation layer is formed, which fills gaps between the first capacitor wires.