Patents by Inventor Hai-Han Hung
Hai-Han Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9985105Abstract: The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.Type: GrantFiled: June 30, 2016Date of Patent: May 29, 2018Assignee: Nanya Technology CorporationInventors: Shin-Yu Nieh, Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee
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Publication number: 20160351678Abstract: The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.Type: ApplicationFiled: June 30, 2016Publication date: December 1, 2016Inventors: Shin-Yu Nieh, Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee
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Patent number: 9349736Abstract: The instant disclosure relates to a method for manufacturing high-strength structural stacked capacitor. The novel feature of the instant disclosure is forming a part of upper electrode layer to cover the first/outer surface of each of the lower electrode layers before removing the sacrificial layer, and forming another part of upper electrode layer to cover the second/inner surface of each of the lower electrode layers after removing the sacrificial layer. Hence, the structure strength of the lower electrode layer in all process steps has been improved.Type: GrantFiled: March 28, 2014Date of Patent: May 24, 2016Assignee: Inotera Memories, Inc.Inventors: Hai-Han Hung, Yi-Ren Lin
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Publication number: 20150348963Abstract: A semiconductor structure includes a substrate having thereon a conductive region, at least one cylinder-shaped container on the conductive region, and a supporting structure having at least two stripe shaped portions arranged in parallel to each other and at least one retaining ring between the two stripe shaped portions. The retaining ring retains and structurally supports the cylinder-shaped container electrode.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: INOTERA MEMORIES, INC.Inventors: Hai-Han Hung, Ping-Hung Kuo, Yi-Wei Chuang
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Publication number: 20150171088Abstract: The instant disclosure relates to a method for manufacturing high-strength structural stacked capacitor. The novel feature of the instant disclosure is forming a part of upper electrode layer to cover the first/outer surface of each of the lower electrode layers before removing the sacrificial layer, and forming another part of upper electrode layer to cover the second/inner surface of each of the lower electrode layers after removing the sacrificial layer. Hence, the structure strength of the lower electrode layer in all process steps has been improved.Type: ApplicationFiled: March 28, 2014Publication date: June 18, 2015Applicant: INOTERA MEMORIES, INC.Inventors: HAI-HAN HUNG, YI-REN LIN
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Patent number: 9029255Abstract: A method for fabricating a semiconductor device is provided. A first polysilicon layer of a first conductivity type is provided on a substrate having first and second active regions. An ion implantation process is performed in the polysilicon layer corresponding to the second active region by using a dopant of a second conductivity type opposite to the first conductivity type, and silane plasma is introduced during the ion implantation process to form a second polysilicon layer thereon and convert the first conductivity type of the first polysilicon layer corresponding to the second active region to the second conductivity type. The first and second polysilicon layers are patterned to form a first gate layer corresponding to the first active region and a second gate layer corresponding to the second active region. A semiconductor device is also provided.Type: GrantFiled: August 24, 2012Date of Patent: May 12, 2015Assignee: Nanya Technology CorporationInventors: Yu-Wei Liang, Hai-Han Hung, Pei-Chi Wu
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Publication number: 20140264640Abstract: The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicant: NANYA TECHNOLOGY CORP.Inventors: Shin-Yu Nieh, Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee
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Patent number: 8697316Abstract: A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.Type: GrantFiled: June 11, 2012Date of Patent: April 15, 2014Assignee: Nanya Technology Corp.Inventors: Ya-Chih Wang, Hai-Han Hung, Wen-Chieh Wang
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Publication number: 20140054720Abstract: A method for fabricating a semiconductor device is provided. A first polysilicon layer of a first conductivity type is provided on a substrate having first and second active regions. An ion implantation process is performed in the polysilicon layer corresponding to the second active region by using a dopant of a second conductivity type opposite to the first conductivity type, and silane plasma is introduced during the ion implantation process to form a second polysilicon layer thereon and convert the first conductivity type of the first polysilicon layer corresponding to the second active region to the second conductivity type. The first and second polysilicon layers are patterned to form a first gate layer corresponding to the first active region and a second gate layer corresponding to the second active region. A semiconductor device is also provided.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Yu-Wei Liang, Hai-Han Hung, Pei-Chi Wu
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Publication number: 20130330660Abstract: A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.Type: ApplicationFiled: June 11, 2012Publication date: December 12, 2013Inventors: Ya-Chih Wang, Hai-Han Hung, Wen-Chieh Wang
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Patent number: 8216946Abstract: A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.Type: GrantFiled: June 23, 2009Date of Patent: July 10, 2012Assignee: Nanya Technology CorporationInventors: Wei-Cheng Shiu, Hai-Han Hung, Ya-Chih Wang, Chien-Mao Liao, Shing-Yih Shih
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Publication number: 20100323521Abstract: A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.Type: ApplicationFiled: June 23, 2009Publication date: December 23, 2010Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Wei-Cheng Shiu, Hai-Han Hung, Ya-Chih Wang, Chien-Mao Liao, Shing-Yih Shih
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Patent number: 7696075Abstract: A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess.Type: GrantFiled: March 25, 2008Date of Patent: April 13, 2010Assignee: Nanya Technology CorporationInventors: Chien-An Yu, Te-Yin Chen, Hai-Han Hung
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Patent number: 7666792Abstract: The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.Type: GrantFiled: February 22, 2008Date of Patent: February 23, 2010Assignee: Nanya Technology Corp.Inventors: Chung-Yen Chou, Hai-Han Hung, Teng-Wang Huang, Shin-Yu Nieh
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Publication number: 20090148993Abstract: A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess.Type: ApplicationFiled: March 25, 2008Publication date: June 11, 2009Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Chien-An Yu, Te-Yin Chen, Hai-Han Hung
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Publication number: 20090130853Abstract: The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.Type: ApplicationFiled: February 22, 2008Publication date: May 21, 2009Inventors: Chung-Yen Chou, Hai-Han Hung, Teng-Wang Huang, Shin-Yu Nieh
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Patent number: 6992021Abstract: A method of forming a silicon nitride layer. The method comprises providing a substrate having a silicon surface thereon, performing an ion implant process on the silicon surface, implanting nitrogen atoms into the silicon surface, and performing a thermal nitridation process and forming a silicon nitride layer on the substrate, wherein the silicon nitride layer comprises the silicon nitride formed on the silicon surface by reaction of the silicon surface with the nitrogen atoms contained therein.Type: GrantFiled: July 16, 2003Date of Patent: January 31, 2006Assignee: Nanya Technology CorporationInventors: Shian-Jyh Lin, Hai-Han Hung, Chung-Yuan Lee
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Publication number: 20050191564Abstract: A method for producing a liner mask on a semiconductor structure is disclosed. The method may include providing an amorphous liner layer (55) on the top side (OS;OS?) of the semiconductor structure, annealing the amorphous liner layer (55) to increase the crystallisation and generate a semi-crystalline liner layer (55); implanting (I1) extrinsic ions in a subregion (55a) of the semi-crystalline liner layer (55) to decrease the etching rate of the subregion (55a) and create an etch selectivity between the to the subregion (55a) complementary subregion (55b) and the subregion (55a) in the predetermined etchant; and selectively removing of the to the subregion (55a) complementary subregion (55b) opposite to the subregion (55a) in a etching step in the predetermined etchant for completing the liner mask.Type: ApplicationFiled: February 27, 2004Publication date: September 1, 2005Inventors: Teng-Wang Huang, Kristin Schupke, Hai-Han Hung
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Publication number: 20040082200Abstract: A method of forming a silicon nitride layer. The method comprises providing a substrate having a silicon surface thereon, performing an ion implant process on the silicon surface, implanting nitrogen atoms into the silicon surface, and performing a thermal nitridation process and forming a silicon nitride layer on the substrate, wherein the silicon nitride layer comprises the silicon nitride formed on the silicon surface by reaction of the silicon surface with the nitrogen atoms contained therein.Type: ApplicationFiled: July 16, 2003Publication date: April 29, 2004Applicant: Nanya Technology CorporationInventors: Shian-Jyh Lin, Hai-Han Hung, Chung-Yuan Lee
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Patent number: 6417064Abstract: A method of treating the surface of a deep trench is disclosed. After forming a deep trench in a silicon substrate, the silicon substrate near the surfaces of the deep trench is treated to become amorphous. An annealing process is executed to make the amorphous silicon layer recrystallize into its original lattice arrangement, so as to reduce lattice defects in the surface of the deep trench.Type: GrantFiled: May 2, 2001Date of Patent: July 9, 2002Assignee: Nanya Technology CorporationInventors: Shian-Jyh Lin, Hai-Han Hung