Abstract: Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.

Abstract: Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.

Abstract: A stack package has a lead frame and first and second stacked chips. The lead frame comprises first and second lead groups respectively corresponding to the first and second chips and a plurality of external connection terminals for electrically interconnecting the first and second chips to an external device. Each of the first and second chips has its own common and independent electrode pads, and each of the first and second lead groups has its own common and independent leads. The common leads and the common electrode pads are for address and control signals to and from the first and second chips, and the independent leads and the independent electrode pads are for data input and output to and from the first and second chips.

Abstract: A stack package has a lead frame and first and second stacked chips. The lead frame comprises first and second lead groups respectively corresponding to the first and second chips and a plurality of external connection terminals for electrically interconnecting the first and second chips to an external device. Each of the first and second chips has its own common and independent electrode pads, and each of the first and second lead groups has its own common and independent leads. The common leads and the common electrode pads are for address and control signals to and from the first and second chips, and the independent leads and the independent electrode pads are for data input and output to and from the first and second chips.

Abstract: Dual-lead type substantially square semiconductor packages and dual in-line memory modules using them are disclosed. The conventional memory module is internationally standardized, so it is hard to increase memory density by adding current packages to the module. The substantially square semiconductor packages provide improved and smaller packages in which a package length and a pin pitch are reduced, so that the memory density is increased without modifying a module size. The length of the leads are preferably substantially equal.

Abstract: A method for manufacturing a chip scale package comprises preparing a tape wiring board that includes a polyimide tape having top and bottom surfaces, Cu traces formed on the bottom surface of the tape, a window formed in the tape to enable the Cu traces to be connected to a semiconductor chip attached below the board, multiple connection holes formed in the tape to expose portions of the Cu traces therethrough and define solder ball mounting pads, and an elastomer chip carrier attached to the bottom surface of the tape. The method includes applying either a pre-flux or a cover sheet over the solder ball mounting pads. The pre-flux and the cover sheet each prevents the solder ball mounting pads being plated with gold. This, in turn, prevents the formation of intermetallic compounds in the solder balls so that the bond strength between the solder balls and a pad to which they attach is improved.

Abstract: A method for manufacturing a chip scale package comprises preparing a tape wiring board that includes a polyimide tape having top and bottom surfaces, Cu traces formed on the bottom surface of the tape, a window formed in the tape to enable the Cu traces to be connected to a semiconductor chip attached below the board, multiple connection holes formed in the tape to expose portions of the Cu traces therethrough and define solder ball mounting pads, and an elastomer chip carrier attached to the bottom surface of the tape. The method includes applying either a pre-flux or a cover sheet over the solder ball mounting pads. The pre-flux and the cover sheet each prevents the solder ball mounting pads being plated with gold. This, in turn, prevents the formation of intermetallic compounds in the solder balls so that the bond strength between the solder balls and a pad to which they attach is improved.

Abstract: A method for bonding a semiconductor chip to a lead frame in a LOC type semiconductor package in which a plurality of inner leads are bonded to an active surface of the semiconductor chip. A semiconductor chip is prepared with a partially-cured polyimide layer on the active surface. One or more strips of polyimide tape is attached to the inner leads. The semiconductor chip is attached to the inner leads by making an intermediate pressure bond between the polyimide tape and the partially-cured polyimide coating layer on the active surface. The polyimide coating layer is then cured.

Abstract: Lead frames for semiconductor chips include spaced apart tie-bars which extend to contact and support the semiconductor chip. Adhesive is used between the tie-bars and the chip to adhesively couple the tie-bars to the chip. The lead frame leads therefore need not be used to adhesively couple the chip to the lead frame, thereby reducing or eliminating the need for equal spacing and close coupling of the leads, and reducing or preventing problems caused by deterioration of adhesive on the leads. The tie-bars may include polyimide tape or liquid adhesive held in cups. During fabrication, a semiconductor chip is mounted on the adhesive material, such that the tie-bars mechanically support the semiconductor chip and the lead ends extend adjacent the semiconductor chip. The lead ends are then electrically connected to the semiconductor chip and the package is encapsulated.

Abstract: Disclosed is a semiconductor device wherein the down bonding and the mounting of multi-pin is made possible. A conductive member adhered to the bottom surface of the semiconductor element. The conductive member and the specific pad of the semiconductor element are connected by the connecting member, which enables the entire bottom surface of the semiconductor element to be used for down bonding. Further, the more effective latch-up suppression, noise dispersion and speed improvement compared with the conventional LOC-type package structure is possible.