Patents by Inventor Hai Jiang

Hai Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040052117
    Abstract: The memory elements with ultra-small resistive element are fabricated by filling the resistive element material in a nano-size opening. To make nano-size opening, a layer of composite-phase thin film is formed where a phase forms nano-size particles and embedded in another phase which forms a matrix layer. Then the nano-size opening was formed by etching the nano-size particles.
    Type: Application
    Filed: June 27, 2003
    Publication date: March 18, 2004
    Inventor: Hai Jiang
  • Publication number: 20040026682
    Abstract: A non-volatile resistive memory comprises of a nano-dot resistive element where the nano-dot acts as a resistive element or small heater. The nano-dot has a size in the range of 1-50 nm. The resistance value of nano-dot resistive element was changed by the atomic configuration of the nano-dot or resistive layer by a suitable pulse current flowing through the nano-dot to realize the storage of the information.
    Type: Application
    Filed: June 3, 2003
    Publication date: February 12, 2004
    Inventor: Hai Jiang
  • Patent number: 6653227
    Abstract: A new method for forming a high quality cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A thermal oxide layer is grown overlying the semiconductor substrate. A titanium layer is deposited overlying the thermal oxide layer. A cobalt layer is deposited overlying the titanium layer. A titanium nitride capping layer is deposited over the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. The substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: November 25, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chung Woh Lai, Beichao Zhang, Eng Hua Lim, Arthur Ang, Hai Jiang Peng, Charles Lin