Abstract: A monitoring system based on a digital converter station includes a first monitoring terminal deployed at a first-level monitoring side, a second monitoring terminal deployed at a second-level monitoring side, and a third monitoring terminal deployed at a third-level monitoring side; the monitoring terminal at each level includes a communication module, a human-machine interaction module, a device status monitoring module, a device alarm management module, a video fusion processing module, and a data transmission adjustment and control module.

Abstract: The present application relates to compounds of Formula (I), as defined herein, and pharmaceutically acceptable salts thereof. The present application also describes pharmaceutical composition comprising a compound of Formula (I), and pharmaceutically acceptable salts thereof, and methods of using the compounds and compositions for treating diseases, such as cancer, autoimmune disorders, and inflammatory disorders.

Abstract: A control circuit for an isolated power supply is disclosed, the control circuit includes a secondary-side drive signal generator, a secondary-side transistor switch turn-off detector and a primary-side control signal generator. The primary-side control signal generator is configured to: determine a second turn-on instant referring to an turn-off instant of the secondary-side synchronous rectification transistor from the turn-off acknowledgement signal; determine a first turn-on instant referring to a supposed turn-on instant for the primary-side transistor switch from the feedback signal of the output voltage of the isolated power supply; and determine the turn-on instant for the primary-side transistor switch from the second turn-on instant or the first turn-on instant whichever is later, and responsively generate the primary-side transistor switch control signal.

Abstract: Isolated power supply control circuits, isolated power supply and control method thereof are disclosed, the control circuit for controlling an isolated power supply includes a secondary-side control signal generator and a primary-side control signal generator. The secondary-side control signal generator produces a secondary-side transistor switch control signal containing information about a turn-off instant of a secondary-side synchronous rectification transistor, which serves as a second turn-on instant. The primary-side control signal generator derives, from a feedback signal, a supposed turn-on instant for a primary-side transistor switch, which serves as a first turn-on instant. The primary side turn-on signal generator further derives a turn-on instant for the primary-side transistor switch from the second or first turn-on instant whichever is later and responsively generates a primary-side transistor switch control signal.

Abstract: The present disclosure relates to a processor and a computing system. A processor is provided, including: a pipeline stage, including sequential device(s); and a first clock driving circuit, configured to provide a clock signal to the pipeline stage, wherein the first clock driving circuit includes: a plurality of first clock paths, configured to provide corresponding clock signals respectively; a first selector, configured to select a clock signal from the clock signals provided by the plurality of first clock paths for the pipeline stage.

Abstract: A method and device for smoke or fire recognition, a computer device and a storage medium are disclosed. The method includes: acquiring a to-be-recognized image in a smoke or fire monitoring region; recognizing a smoke or fire suspected region in the to-be-recognized image according to the to-be-recognized image, including recognizing a smoke or fire suspected region in a visible light image on the basis of colors, and recognizing a smoke or fire suspected region in an infrared image on the basis of brightness; and inputting the to-be-recognized image including the smoke or fire suspected region into a preset model, and recognizing a smoke or fire state in the to-be-recognized image according to an output result of the preset model, the preset model being obtained by training based on the visible light image pre-marked with a smoke or fire state or the infrared image pre-marked with a smoke or fire state.

Abstract: A hashboard, a power supply system of a digital processing device and the digital processing device. The digital processing device comprises: a housing; N (>2) hashboards and a control board both located inside the housing. Each hashboard comprises: a substrate; power positive and power negative terminals respectively mounted on the substrate and adapted to be connected to another hashboard in series; a communication interface mounted on the substrate; and computing chips mounted on the substrate. A signal transfer path of the computing chips has a chain configuration. The N hashboards are connected in series to form a series power supply configuration, a power positive terminal of a first hashboard in the series power supply configuration is connected to a positive terminal of a power supply, and a power negative terminal of a last hashboard in the series power supply configuration is connected to a negative terminal of the power supply.

Abstract: A computing device and a computing system for digital currency are disclosed. The computing system comprises: computing devices (comprising first and second computing devices) each comprising two ports; and a signal transmission path connecting the computing devices in series. Each computing device is connected to the signal transmission path via the two ports. The first computing device is configured to receive, from the signal transmission path through one of the two ports, a signal specific to an address of the first computing device to a local storage device thereof. The second computing device is configured to receive, from the signal transmission path through one of the two ports, a signal to a local storage device thereof, and forward the signal, which is not specific to an address of the second computing device, or an adjusted version of the signal to the signal transmission path through one of the ports.

Abstract: Disclosed is a method for determining configuration parameters of a data processing device, including: operating the data processing device by using configuration parameters, which are universal optimization configuration parameters obtained according to a universal operating parameter model; during the operating process, changing the configuration parameters to obtain a dedicated operating parameter data set which includes a plurality of groups of operating parameters, and-each of which includes configuration parameters and capability parameters of the data processing device when the data processing device is operating under the configuration parameters; executing model training by using the dedicated operating parameter data set to obtain a dedicated operating parameter model; and obtaining optimal configuration parameters according to the dedicated operating parameter model, and operating the data processing device according to the optimal configuration parameters, where the optimal configuration parameter

Abstract: The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.

Abstract: A computing device and a computing system are provided. The computing device comprises: a plurality of computing modules; and serial communication paths between/among the plurality of computing modules. Each computing module comprises: an internal circuit for performing an operation on a signal received from a corresponding serial communication path; and an extension circuit for receiving a signal from the internal circuit as an input signal. The extension circuit comprises: a delay module for delaying the input signal, the delay module comprising one or more delay units; one or more extension select modules for selectively performing a level extension on the input signal through the signal delayed by corresponding one or more delay units to generate one or more respective level-extended signals; and an output module for outputting one or more of the one or more level-extended signals.

Abstract: The present disclosure relates to clock circuits, computing chips, hash boards and data processing devices. A clock circuit comprises M stages of clock drive circuits that are connected in series, M being an integer that is no less than 2, wherein N inverters connected in series are arranged between an input port and an output port of each stage of the M stages of clock drive circuits, N being an odd number that is no less than 3. The clock circuit may provide clock signals with excellent performance.

Abstract: A dynamic D flip-flop with an inverted output involves an input end (101) used for receiving input data; an output end (102) used for providing output data to respond to the input data; a clock signal end (103) used for receiving a clock signal; a first latch (104) used for latching the input data from the input end (101) and performing inverting transmission on the input data under the control of the clock signal; a second latch (105) used for latching data from the first latch (104) and performing inverting transmission on the data latched by the first latch (104) under the control of the clock signal; and an inverter (106) used for performing inverting output on the data received from the second latch (105), the first latch (104), the second latch (105), and the inverter (106) being sequentially connected in series between the input end and the output end.

Abstract: A data processing device and a data processing system are provided. The data processing device includes a housing, which is thermally conductive and defines a sealed accommodating cavity; a hashboard, which is arranged in the accommodating cavity and is in fixed connection to the housing; a control board, which is in communicative connection to the hashboard; and a power supply module, which is in electrical connection to the hashboard.

Abstract: An electronic device includes an arithmetic unit layer and a power supply. The arithmetic unit layer comprises at least one arithmetic unit. Each arithmetic unit comprises a first housing in shape of cuboid. The height direction of the first housing extends in a first direction. The width direction extends in a second direction perpendicular to the first direction. The first housing is provided with first and second openings at both ends in the height direction to form a coolant passage extending in the first direction. The power supply and arithmetic unit layer are laminated in the second or a third direction. The height direction of the power supply is aligned with the height direction of each arithmetic unit. The power supply is provided with third and fourth openings at both ends in the height direction to form a coolant passage extending in the height direction of the power supply.

Abstract: A computing device and a series power supply method are disclosed. The computing device includes: a hash board, including a series power supply circuit, which includes m layers of to-be-powered chips that are connected in series between a power supply positive electrode and a power supply negative electrode of the hash board, wherein highest-layer to-be-powered chips are connected to the power supply positive electrode, and bottommost-layer to-be-powered chips are connected to the power supply negative electrode, wherein the power supply positive electrode is configured to receive a higher potential relative to the power supply negative electrode; a control board, configured to provide, to the hash board, control signals and communication signals that are accessed to the series power supply circuit through a communication interface of the highest-layer to-be-powered chips and communicated to lower layers through the m layers of to-be-powered chips that are connected in series.

Abstract: Implementations of this application provide a method and an apparatus for controlling a voltage of a power supply of a data processing device and a data processing device. The method includes: determining a computing power ratio of the data processing device based on an actual computing power and a theoretical computing power of the data processing device; generating a power supply control instruction based on a result of comparison between the computing power ratio and a predetermined threshold; and controlling an output voltage of the power supply of the data processing device based on the power supply control instruction. According to the implementations of this application, the output voltage of the power supply is controlled according to the computing power ratio, and a good compromise can be obtained between the power consumption loss and the computing power of the data processing device.

Abstract: This application discloses a liquid cooling plate radiator and a computing device adopting the liquid cooling plate radiator. The liquid cooling plate radiator includes: a radiator body; and a cooling liquid flow channel located in the radiator body, wherein a width of the cooling liquid flow channel is not less than a width of at least two chips arranged.

Abstract: A computing device and a series power supply method are disclosed. The computing device includes: a hash board, including a series power supply circuit, which includes m layers of to-be-powered chips that are connected in series between a power supply positive electrode and a power supply negative electrode of the hash board, wherein highest-layer to-be-powered chips are connected to the power supply positive electrode, and bottommost-layer to-be-powered chips are connected to the power supply negative electrode, wherein the power supply positive electrode is configured to receive a higher potential relative to the power supply negative electrode; a control board, configured to provide, to the hash board, control signals and communication signals that are accessed to the series power supply circuit through a communication interface of the highest-layer to-be-powered chips and communicated to lower layers through the m layers of to-be-powered chips that are connected in series.

Abstract: The present disclosure relates to a method for providing clock frequencies for computing cores, a chip and a data processing device. The method includes: causing a main clock frequency unit to provide a first main clock frequency for computing cores; testing the computing cores operating at the first main clock frequency to determine whether a pass rate of the computing cores is greater than an upper threshold or less than a lower threshold; when the pass rate is less than the lower threshold, causing an auxiliary clock frequency unit to provide a lower first auxiliary clock frequency for computing cores abnormally operating, causing the main clock frequency unit to providing the first main clock frequency for the remaining computing cores; when the pass rate is greater than the upper threshold, causing the main clock frequency unit to provide a higher second main clock frequency for the computing cores.