Abstract: Systems, computer-implemented methods, and computer program products to aggregate classifier result are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a fractal dividing component that can train classifiers with fractally defined disjoint and non-disjoint subsets of training data comprising data with a first label and data with a second label. Further, the system can include training component that can train the group of classifiers with the fractally defined disjoint and non-disjoint subsets of training data. A fractal aggregating component can be included to generate a unified result of the classifiers by fractally aggregating results of classification by the ones of the classifiers, based on the subsets.

Abstract: A training method, system, and computer program product include training a neural network including at least one of using norm-pooling as a non-linear function, using a two-sided ReLU as a non-linear function, and increasing a confidence gap and further training such that the network comprises a non-expansive network.

Abstract: Technologies for a neural belief reasoner model generative models that specifies belief functions are described. Aspects include receiving, by a device operatively coupled to a processor, a request for a belief function, and processing, by the device, the request for the belief function in the generative model based on trained probability parameters and a minimization function to determine a generalized belief function defined by fuzzy sets. Data corresponding to the generalized belief function is output, e.g., as a belief value and plausibility value.

Abstract: A training method, system, and computer program product include training a neural network including using two-sided ReLU as a non-linear function or norm-pooling as a non-linear function and increasing a confidence gap.

Abstract: The present invention discloses a method for preparing bread by fermentation with compounded sourdough, and belongs to the technical field of food. The method compounds saccharomycetes and lactic acid bacteria to prepare the compounded sourdough. Compared with spontaneous sourdough, the fermentation performance is similar, the quality is stable, the culture period is shortened, and the compounded sourdough can be used to replace the spontaneous sourdough to prepare bread by fermentation. Moreover, the nutritional value of the compounded sourdough bread is much higher than that of the commercial yeast bread using only a single type of yeast, both in terms of the total content of free amino acids and the content of essential amino acids. The compounded sourdough provided by the present invention has extremely high industrial application value.

Abstract: Techniques for improved neural network modeling are provided. In one embodiment, a system comprises a memory that stores computer-executable components and a processor that executes the components. The computer-executable components can comprise a loss function logic component that determines a penalty based on a training term, the training term being a function of a relationship between an output scalar value of a first neuron of a plurality of neurons of a neural network model, a plurality of input values from the first neuron, and one or more tunable weights of connections between the plurality of neurons; an optimizer component that receives the penalty from the loss function component, and changes one or more of the tunable weights based on the penalty; and an output component that generates one or more output values indicating whether a defined pattern is detected in unprocessed input values received at the neural network evaluation component.

Abstract: Systems, computer-implemented methods, and computer program products to aggregate classifier result are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a fractal dividing component that can train classifiers with fractally defined disjoint and non-disjoint subsets of training data comprising data with a first label and data with a second label. Further, the system can include training component that can train the group of classifiers with the fractally defined disjoint and non-disjoint subsets of training data. A fractal aggregating component can be included to generate a unified result of the classifiers by fractally aggregating results of classification by the ones of the classifiers, based on the subsets.

Abstract: A training method, system, and computer program product include computing a matrix norm over a product of a weight matrix and a transpose of the weight matrix and using the matrix norm to constrain the L2 non-expansive neural network.

Abstract: The present disclosure discloses a brown rice and oat bread with low glycemic index and a preparation method thereof, which belongs to the technical field of grain processing. The brown rice and oat bread provided by the present disclosure includes the following ingredients: brown rice flour, gluten powder, oat flour, butter, sodium caseinate, salt, yeast, improver, and water. According to the present disclosure, the sodium caseinate is used to help form a dough and improve the flavor of the bread, and the brown rice and oat bread with low glycemic index is obtained with the brown rice bread recipe and special baking process, which is close to wheat bread in terms of specific volume, taste and tissue structure.

Abstract: A computer system, computer program product, and computer implemented method to enhance robustness an artificial neural network through obfuscation. One or more high frequency and low amplitude elements are added to the artificial neural network. The added elements provide a defense mechanism to the artificial network, thereby functioning as a security mechanism against an adversarial attack.

Abstract: Mechanisms, in a system comprising a host system and at least one accelerator device, for performing a concept analysis operation are provided. The host system extracts a set of one or more concepts from an information source and provides the set of one or more concepts to the accelerator device. The host system also provides at least one matrix representation data structure representing a graph of concepts and relationships between concepts in a corpus. The accelerator device executes the concept analysis operation internal to the accelerator device to generate an output vector identifying concepts in the corpus, identified in the at least one matrix representation data structure, related to the set of one or more concepts extracted from the information source. The accelerator device outputs the output vector to the host system which utilizes the output vector to respond to a request submitted to the host system associated with the information source.

Abstract: An integrated circuit (IC) includes: a plurality of hardware performance counters; a thermal sensor; and a micro-controller. The micro-controller generates a plurality of thermal predictors based on values of the counters and temperatures sensed by the thermal sensor. The thermal predictors include first and second rising thermal delta predictors to predict rising temperature deltas and first and second falling thermal delta predictors to predict falling temperature deltas. The micro-controller predicts a future temperature of the IC based on an idle temperature of the IC and a selected one of the temperature deltas.

Abstract: A training method, system, and computer program product include training a neural network including using two-sided ReLU as a non-linear function or norm-pooling as a non-linear function and increasing a confidence gap.

Abstract: A training method, system, and computer program product include computing a matrix norm over a product of a weight matrix and a transpose of the weight matrix and using the matrix norm to constrain the L2 non-expansive neural network.

Abstract: A training method, system, and computer program product include training a neural network including at least one of using norm-pooling as a non-linear function, using a two-sided ReLU as a non-linear function, and increasing a confidence gap and further training such that the network comprises a non-expansive network.

Abstract: A method and system to perform clock network analysis of a clock network of an integrated circuit that includes a grid obtains parameters for each transmission line of the clock network that carries a clock signal between a source of the clock signal and the grid. The method also includes obtaining models of nonlinear components of the clock network, and numerically solving a frequency domain nonlinear Harmonic Balance equation to obtain voltage values at an input and an output of each of the nonlinear components. The number of the voltage values obtained is proportional to the number of the nonlinear components. A physical implementation of the integrated circuit is obtained based on the clock network analysis.

Abstract: An integrated circuit (IC) includes: a plurality of hardware performance counters; a thermal sensor; and a micro-controller. The micro-controller generates a plurality of thermal predictors based on values of the counters and temperatures sensed by the thermal sensor. The thermal predictors include first and second rising thermal delta predictors to predict rising temperature deltas and first and second falling thermal delta predictors to predict falling temperature deltas. The micro-controller predicts a future temperature of the IC based on an idle temperature of the IC and a selected one of the temperature deltas.

Abstract: An integrated circuit (IC) includes: a plurality of hardware performance counters; a thermal sensor; and a micro-controller. The micro-controller generates a plurality of thermal predictors based on values of the counters and temperatures sensed by the thermal sensor. The thermal predictors include first and second rising thermal delta predictors to predict rising temperature deltas and first and second falling thermal delta predictors to predict falling temperature deltas. The micro-controller predicts a future temperature of the IC based on an idle temperature of the IC and a selected one of the temperature deltas.

Abstract: The present invention discloses a method for preparing bread by fermentation with compounded sourdough, and belongs to the technical field of food. The method compounds saccharomycetes and lactic acid bacteria to prepare the compounded sourdough. Compared with spontaneous sourdough, the fermentation performance is similar, the quality is stable, the culture period is shortened, and the compounded sourdough can be used to replace the spontaneous sourdough to prepare bread by fermentation. Moreover, the nutritional value of the compounded sourdough bread is much higher than that of the commercial yeast bread using only a single type of yeast, both in terms of the total content of free amino acids and the content of essential amino acids. The compounded sourdough provided by the present invention has extremely high industrial application value.

Abstract: Mechanisms, in a system comprising a host system and at least one accelerator device, for performing a concept analysis operation are provided. The host system extracts a set of one or more concepts from an information source and provides the set of one or more concepts to the accelerator device. The host system also provides at least one matrix representation data structure representing a graph of concepts and relationships between concepts in a corpus. The accelerator device executes the concept analysis operation internal to the accelerator device to generate an output vector identifying concepts in the corpus, identified in the at least one matrix representation data structure, related to the set of one or more concepts extracted from the information source. The accelerator device outputs the output vector to the host system which utilizes the output vector to respond to a request submitted to the host system associated with the information source.