Abstract: Mechanisms, in a system comprising a host system and at least one accelerator device, for performing a concept analysis operation are provided. The host system extracts a set of one or more concepts from an information source and provides the set of one or more concepts to the accelerator device. The host system also provides at least one matrix representation data structure representing a graph of concepts and relationships between concepts in a corpus. The accelerator device executes the concept analysis operation internal to the accelerator device to generate an output vector identifying concepts in the corpus, identified in the at least one matrix representation data structure, related to the set of one or more concepts extracted from the information source. The accelerator device outputs the output vector to the host system which utilizes the output vector to respond to a request submitted to the host system associated with the information source.

Abstract: Technologies for a neural belief reasoner model generative models that specifies belief functions are described. Aspects include receiving, by a device operatively coupled to a processor, a request for a belief function, and processing, by the device, the request for the belief function in the generative model based on trained probability parameters and a minimization function to determine a generalized belief function defined by fuzzy sets. Data corresponding to the generalized belief function is output, e.g., as a belief value and plausibility value.

Abstract: Mechanisms, in a system comprising a host system and at least one accelerator device, for performing a concept analysis operation are provided. The host system extracts a set of one or more concepts from an information source and provides the set of one or more concepts to the accelerator device. The host system also provides at least one matrix representation data structure representing a graph of concepts and relationships between concepts in a corpus. The accelerator device executes the concept analysis operation internal to the accelerator device to generate an output vector identifying concepts in the corpus, identified in the at least one matrix representation data structure, related to the set of one or more concepts extracted from the information source. The accelerator device outputs the output vector to the host system which utilizes the output vector to respond to a request submitted to the host system associated with the information source.

Abstract: Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of an input matrix. An input matrix, which comprises nodes associated with elements of the matrix, is received. The nodes are clustered into clusters based on numbers of connections with other nodes within and between the clusters, and the clusters are ordered by minimizing a total length of cross cluster connections between nodes of the clusters, to thereby generate a reordered matrix. A lookup table is generated identifying new locations of nodes of the input matrix, in the reordered matrix. A matrix operation is then performed based on the reordered matrix and the lookup table.

Abstract: Techniques for improved neural network modeling are provided. In one embodiment, a system comprises a memory that stores computer-executable components and a processor that executes the components. The computer-executable components can comprise a loss function logic component that determines a penalty based on a training term, the training term being a function of a relationship between an output scalar value of a first neuron of a plurality of neurons of a neural network model, a plurality of input values from the first neuron, and one or more tunable weights of connections between the plurality of neurons; an optimizer component that receives the penalty from the loss function component, and changes one or more of the tunable weights based on the penalty; and an output component that generates one or more output values indicating whether a defined pattern is detected in unprocessed input values received at the neural network evaluation component.

Abstract: A method and system to perform clock network analysis of a clock network of an integrated circuit that includes a grid obtains parameters for each transmission line of the clock network that carries a clock signal between a source of the clock signal and the grid. The method also includes obtaining models of nonlinear components of the clock network, and numerically solving a frequency domain nonlinear Harmonic Balance equation to obtain voltage values at an input and an output of each of the nonlinear components. The number of the voltage values obtained is proportional to the number of the nonlinear components. A physical implementation of the integrated circuit is obtained based on the clock network analysis.

Abstract: Mechanisms are provided for performing a cognitive operation. An input graph is received having a plurality of first nodes, where subsets of first nodes are coupled to one another via first edges and each first edge has an associated weight. A blinking graph model is generated based on the graph, where blink rates are associated with second edges and are calculated based on weights of corresponding first edges in the input graph. The blink rate specifies a fraction of time a corresponding second edge is determined to be present in the blinking graph model. A relatedness metric is calculated for a target node relative to a node of interest based on the blink rates of the second edges. The relatedness metric indicates a degree of relatedness of the target node to the node of interest. A cognitive operation is then performed based on the relatedness metric.

Abstract: Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.

Abstract: An integrated circuit (IC) includes: a plurality of hardware performance counters; a thermal sensor; and a micro-controller. The micro-controller generates a plurality of thermal predictors based on values of the counters and temperatures sensed by the thermal sensor. The thermal predictors include first and second rising thermal delta predictors to predict rising temperature deltas and first and second falling thermal delta predictors to predict falling temperature deltas. The micro-controller predicts a future temperature of the IC based on an idle temperature of the IC and a selected one of the temperature deltas.

Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.

Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.

Abstract: Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.

Abstract: Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of an input matrix. An input matrix, which comprises nodes associated with elements of the matrix, is received. The nodes are clustered into clusters based on numbers of connections with other nodes within and between the clusters, and the clusters are ordered by minimizing a total length of cross cluster connections between nodes of the clusters, to thereby generate a reordered matrix. A lookup table is generated identifying new locations of nodes of the input matrix, in the reordered matrix. A matrix operation is then performed based on the reordered matrix and the lookup table.

Abstract: Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.

Abstract: Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of an input matrix. An input matrix, which comprises nodes associated with elements of the matrix, is received. The nodes are clustered into clusters based on numbers of connections with other nodes within and between the clusters, and the clusters are ordered by minimizing a total length of cross cluster connections between nodes of the clusters, to thereby generate a reordered matrix. A lookup table is generated identifying new locations of nodes of the input matrix, in the reordered matrix. A matrix operation is then performed based on the reordered matrix and the lookup table.

Abstract: Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.

Abstract: Mechanisms are provided for performing a cognitive operation. An input graph is received having a plurality of first nodes, where subsets of first nodes are coupled to one another via first edges and each first edge has an associated weight. A blinking graph model is generated based on the graph, where blink rates are associated with second edges and are calculated based on weights of corresponding first edges in the input graph. The blink rate specifies a fraction of time a corresponding second edge is determined to be present in the blinking graph model. A relatedness metric is calculated for a target node relative to a node of interest based on the blink rates of the second edges. The relatedness metric indicates a degree of relatedness of the target node to the node of interest. A cognitive operation is then performed based on the relatedness metric.

Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.

Abstract: Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.

Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.