Patents by Inventor Haifeng Zhou
Haifeng Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240077736Abstract: The present disclosure relates to light guides and near-eye display apparatuses. One example light guide includes a light guide plate and a two-dimensional grating that is disposed on a surface of the light guide plate. The two-dimensional grating includes a plurality of grating units arranged in a planar shape, the grating units are arranged at an interval of a first distance along a first direction and at an interval of a second distance along a second direction, and the first direction intersects with the second direction. The two-dimensional grating includes a light egress area and a light ingress area that are arranged along a third direction, and a fourth direction is perpendicular to the third direction.Type: ApplicationFiled: November 14, 2023Publication date: March 7, 2024Inventors: Haifeng ZHOU, Liming LIU, Ziqian DING
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Patent number: 11700004Abstract: A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.Type: GrantFiled: January 28, 2022Date of Patent: July 11, 2023Assignee: ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.Inventor: HaiFeng Zhou
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Publication number: 20220200603Abstract: A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.Type: ApplicationFiled: January 28, 2022Publication date: June 23, 2022Inventor: HaiFeng ZHOU
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Patent number: 11342922Abstract: A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.Type: GrantFiled: December 21, 2020Date of Patent: May 24, 2022Assignee: Advanced Micro Devices, Inc.Inventor: HaiFeng Zhou
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Patent number: 11218152Abstract: A charge pump circuit and phase-locked loop include start, bias, current mirror, charging and discharging feedback control, and charging and discharging matching modules, which are electrically connected in sequence. The start module starts the bias module. The bias module generates constant bias current and outputs same to the current mirror module, which receives and amplifies the bias current for output in two paths. The charging and discharging feedback control module detects the output voltage of a charge pump and controls, according to feedback of the output voltage, the current in the charging and discharging matching module, to suppress the mismatch between charging and discharging currents. The charging and discharging matching module receives an external charging or discharging control signal, to charge or discharge the output load of the charge pump. Charging and discharging currents can be matched within a wide output voltage range, without an operational amplifier.Type: GrantFiled: February 5, 2018Date of Patent: January 4, 2022Assignees: CHINA COMMUNICATION MICROELECTRONICS TECHNOLOGY CO., LTD., CHINA COMMUNICATION TECHNOLOGY CO., LTD.Inventors: Qing Ding, Haifeng Zhou, Guangsheng Wu, Xiaocong Li
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Publication number: 20210402418Abstract: A device and a method for reducing wind resistance power of a large geotechnical centrifuge are provided. A semicircular tube cylindrical cooling device is installed between an internal side of a high-speed rotor system and a cylindrical shell. A serpentine top semicircular tube cooling plate is provided right above a hanging basket, and return helium gas inlet holes are opened at a center of the top semicircular tube cooling plate. A helium gas in a helium gas storage tank passes through helium gas outlets on the helium gas inlet pipes, and enters a centrifuge chamber from a bottom sealing plate. The helium gas is used to replace air in the centrifuge chamber to reduce the wind resistance power and corresponding energy consumption. No vacuuming is required, so sealing requirements are lower. Heat dissipation equipment is placed inside the centrifuge chamber, and a helium gas circulation wind duct is added to improve heat exchange coefficient and heat dissipation effect.Type: ApplicationFiled: November 5, 2019Publication date: December 30, 2021Inventors: Chuanxiang Zheng, Shuang Wei, Haifeng Zhou
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Patent number: 10979317Abstract: A service registration method and usage method, and a related apparatus are used to reduce risks generated when a service of an AP-type service providing node cannot be registered and a CP-type service providing node provides a service since distributed characteristics of a service providing node are not distinguished in a network partition scenario. The method is: obtaining, by a registration service node, network partition information, and receiving a registration request of a service providing node, where the registration request carries a distributed characteristic of the service providing node, and the distributed characteristic meets both consistency and partition tolerance, or meets both availability and partition tolerance; and determining, by the registration service node according to the network partition information and the distributed characteristic of the service providing node, whether registration of a service provided by the service providing node is allowed.Type: GrantFiled: January 22, 2018Date of Patent: April 13, 2021Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Haifeng Zhou, Long Li, Jianqing Yuan
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Patent number: 10868144Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.Type: GrantFiled: May 13, 2019Date of Patent: December 15, 2020Inventors: Runling Li, Haifeng Zhou
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Patent number: 10651285Abstract: The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.Type: GrantFiled: February 10, 2017Date of Patent: May 12, 2020Assignee: Shanghai Huali Microelectronics CorporationInventors: Yingming Liu, Yu Bao, Haifeng Zhou, Jingxun Fang
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Publication number: 20200052705Abstract: A charge pump circuit and phase-locked loop include start, bias, current mirror, charging and discharging feedback control, and charging and discharging matching modules, which are electrically connected in sequence. The start module starts the bias module. The bias module generates constant bias current and outputs same to the current mirror module, which receives and amplifies the bias current for output in two paths. The charging and discharging feedback control module detects the output voltage of a charge pump and controls, according to feedback of the output voltage, the current in the charging and discharging matching module, to suppress the mismatch between charging and discharging currents. The charging and discharging matching module receives an external charging or discharging control signal, to charge or discharge the output load of the charge pump. Charging and discharging currents can be matched within a wide output voltage range, without an operational amplifier.Type: ApplicationFiled: February 5, 2018Publication date: February 13, 2020Inventors: Qing DING, Haifeng ZHOU, Guangsheng WU, Xiaocong LI
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Patent number: 10487265Abstract: Providing a method for pyrolysis treatment of oily sludge and environment-friendly renovation of the residue thereof with humic acid substance. The method relates to inside-mixing solid heat carrier with oily sludge to improve the liquid yield, and completely removing the petroleum hydrocarbons from pyrolyzing residue by calcinating it in a fluidized bed, and using the fractionated large and medium particles as the circulating heat carrier, and discharging the fine particles, and performing environment-friendly renovation with the biological humic acid substance to achieve combinations of the harmless technical measures, thereby achieve harmlessness, reduced quantity and resourceful treatment of the oily sludge.Type: GrantFiled: March 5, 2019Date of Patent: November 26, 2019Assignee: CHINA UNIVERSITY OF PETROLEUM (EAST CHINA)Inventors: Yuanyu Tian, Yingyun Qiao, Kechang Xie, Zhaohe Yang, Haifeng Zhou, Jie Li
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Publication number: 20190347377Abstract: The invention relates to an AlGaN/GaN HEMT small-signal model and a method for extracting parameters thereof. According to the AlGaN/GaN HEMT small-signal model of the invention, based on a conventional AlGaN/GaN HEMT small-signal model, a first coplanar waveguide capacitor (I) between a gate and a source and a second coplanar waveguide capacitor (II) between the gate and a drain are added in a parasitic unit. Since an AlGaN/GaN HEMT device and a coplanar waveguide device have similar structures, by introducing the first coplanar waveguide capacitor (I) and the second coplanar waveguide capacitor (II) under a high-frequency condition, that is, considering the fact that the coplanar waveguide effect of the AlGaN/GaN HEMT device will introduce additional parasitic capacitances, the working state and device characteristics of the AlGaN/GaN HEMT device can be reflected more accurately, and the accuracy of the device model is improved.Type: ApplicationFiled: December 25, 2017Publication date: November 14, 2019Inventors: Guangsheng WU, Haifeng ZHOU, Ging DiNG, Xiaocong LI, Jiaila WANG
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Publication number: 20190322433Abstract: In the context of e-commerce, the packaging system of the present invention provides the necessary protection of consumer goods from rigors of transportation and parcel delivery while providing significant environment and cost savings.Type: ApplicationFiled: March 15, 2019Publication date: October 24, 2019Inventors: Haifeng Zhou, Wanmin Yang
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Publication number: 20190267472Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Inventors: Runling Li, Haifeng Zhou
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Patent number: 10332979Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.Type: GrantFiled: October 8, 2015Date of Patent: June 25, 2019Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Runling Li, Haifeng Zhou
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Patent number: 10276450Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.Type: GrantFiled: February 10, 2017Date of Patent: April 30, 2019Assignee: Shanghai Huali Microelectronics CorporationInventors: Tong Lei, Yongyue Chen, Haifeng Zhou
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Patent number: 10177049Abstract: Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.Type: GrantFiled: March 28, 2018Date of Patent: January 8, 2019Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Haifeng Zhou, Jun Tan
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Publication number: 20180240718Abstract: Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.Type: ApplicationFiled: March 28, 2018Publication date: August 23, 2018Inventors: Haifeng ZHOU, Jun Tan
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Patent number: 10008420Abstract: Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.Type: GrantFiled: April 20, 2015Date of Patent: June 26, 2018Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Haifeng Zhou, Jun Tan
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Publication number: 20180174924Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.Type: ApplicationFiled: February 10, 2017Publication date: June 21, 2018Applicant: Shanghai Huali Microelectronics CorporationInventors: Tong Lei, Yongyue Chen, Haifeng Zhou