Patents by Inventor Haifeng Zhou

Haifeng Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240077736
    Abstract: The present disclosure relates to light guides and near-eye display apparatuses. One example light guide includes a light guide plate and a two-dimensional grating that is disposed on a surface of the light guide plate. The two-dimensional grating includes a plurality of grating units arranged in a planar shape, the grating units are arranged at an interval of a first distance along a first direction and at an interval of a second distance along a second direction, and the first direction intersects with the second direction. The two-dimensional grating includes a light egress area and a light ingress area that are arranged along a third direction, and a fourth direction is perpendicular to the third direction.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 7, 2024
    Inventors: Haifeng ZHOU, Liming LIU, Ziqian DING
  • Patent number: 11700004
    Abstract: A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: July 11, 2023
    Assignee: ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
    Inventor: HaiFeng Zhou
  • Publication number: 20220200603
    Abstract: A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.
    Type: Application
    Filed: January 28, 2022
    Publication date: June 23, 2022
    Inventor: HaiFeng ZHOU
  • Patent number: 11342922
    Abstract: A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 24, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: HaiFeng Zhou
  • Patent number: 11218152
    Abstract: A charge pump circuit and phase-locked loop include start, bias, current mirror, charging and discharging feedback control, and charging and discharging matching modules, which are electrically connected in sequence. The start module starts the bias module. The bias module generates constant bias current and outputs same to the current mirror module, which receives and amplifies the bias current for output in two paths. The charging and discharging feedback control module detects the output voltage of a charge pump and controls, according to feedback of the output voltage, the current in the charging and discharging matching module, to suppress the mismatch between charging and discharging currents. The charging and discharging matching module receives an external charging or discharging control signal, to charge or discharge the output load of the charge pump. Charging and discharging currents can be matched within a wide output voltage range, without an operational amplifier.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 4, 2022
    Assignees: CHINA COMMUNICATION MICROELECTRONICS TECHNOLOGY CO., LTD., CHINA COMMUNICATION TECHNOLOGY CO., LTD.
    Inventors: Qing Ding, Haifeng Zhou, Guangsheng Wu, Xiaocong Li
  • Publication number: 20210402418
    Abstract: A device and a method for reducing wind resistance power of a large geotechnical centrifuge are provided. A semicircular tube cylindrical cooling device is installed between an internal side of a high-speed rotor system and a cylindrical shell. A serpentine top semicircular tube cooling plate is provided right above a hanging basket, and return helium gas inlet holes are opened at a center of the top semicircular tube cooling plate. A helium gas in a helium gas storage tank passes through helium gas outlets on the helium gas inlet pipes, and enters a centrifuge chamber from a bottom sealing plate. The helium gas is used to replace air in the centrifuge chamber to reduce the wind resistance power and corresponding energy consumption. No vacuuming is required, so sealing requirements are lower. Heat dissipation equipment is placed inside the centrifuge chamber, and a helium gas circulation wind duct is added to improve heat exchange coefficient and heat dissipation effect.
    Type: Application
    Filed: November 5, 2019
    Publication date: December 30, 2021
    Inventors: Chuanxiang Zheng, Shuang Wei, Haifeng Zhou
  • Patent number: 10979317
    Abstract: A service registration method and usage method, and a related apparatus are used to reduce risks generated when a service of an AP-type service providing node cannot be registered and a CP-type service providing node provides a service since distributed characteristics of a service providing node are not distinguished in a network partition scenario. The method is: obtaining, by a registration service node, network partition information, and receiving a registration request of a service providing node, where the registration request carries a distributed characteristic of the service providing node, and the distributed characteristic meets both consistency and partition tolerance, or meets both availability and partition tolerance; and determining, by the registration service node according to the network partition information and the distributed characteristic of the service providing node, whether registration of a service provided by the service providing node is allowed.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 13, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Haifeng Zhou, Long Li, Jianqing Yuan
  • Patent number: 10868144
    Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 15, 2020
    Inventors: Runling Li, Haifeng Zhou
  • Patent number: 10651285
    Abstract: The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: May 12, 2020
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Yingming Liu, Yu Bao, Haifeng Zhou, Jingxun Fang
  • Publication number: 20200052705
    Abstract: A charge pump circuit and phase-locked loop include start, bias, current mirror, charging and discharging feedback control, and charging and discharging matching modules, which are electrically connected in sequence. The start module starts the bias module. The bias module generates constant bias current and outputs same to the current mirror module, which receives and amplifies the bias current for output in two paths. The charging and discharging feedback control module detects the output voltage of a charge pump and controls, according to feedback of the output voltage, the current in the charging and discharging matching module, to suppress the mismatch between charging and discharging currents. The charging and discharging matching module receives an external charging or discharging control signal, to charge or discharge the output load of the charge pump. Charging and discharging currents can be matched within a wide output voltage range, without an operational amplifier.
    Type: Application
    Filed: February 5, 2018
    Publication date: February 13, 2020
    Inventors: Qing DING, Haifeng ZHOU, Guangsheng WU, Xiaocong LI
  • Patent number: 10487265
    Abstract: Providing a method for pyrolysis treatment of oily sludge and environment-friendly renovation of the residue thereof with humic acid substance. The method relates to inside-mixing solid heat carrier with oily sludge to improve the liquid yield, and completely removing the petroleum hydrocarbons from pyrolyzing residue by calcinating it in a fluidized bed, and using the fractionated large and medium particles as the circulating heat carrier, and discharging the fine particles, and performing environment-friendly renovation with the biological humic acid substance to achieve combinations of the harmless technical measures, thereby achieve harmlessness, reduced quantity and resourceful treatment of the oily sludge.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 26, 2019
    Assignee: CHINA UNIVERSITY OF PETROLEUM (EAST CHINA)
    Inventors: Yuanyu Tian, Yingyun Qiao, Kechang Xie, Zhaohe Yang, Haifeng Zhou, Jie Li
  • Publication number: 20190347377
    Abstract: The invention relates to an AlGaN/GaN HEMT small-signal model and a method for extracting parameters thereof. According to the AlGaN/GaN HEMT small-signal model of the invention, based on a conventional AlGaN/GaN HEMT small-signal model, a first coplanar waveguide capacitor (I) between a gate and a source and a second coplanar waveguide capacitor (II) between the gate and a drain are added in a parasitic unit. Since an AlGaN/GaN HEMT device and a coplanar waveguide device have similar structures, by introducing the first coplanar waveguide capacitor (I) and the second coplanar waveguide capacitor (II) under a high-frequency condition, that is, considering the fact that the coplanar waveguide effect of the AlGaN/GaN HEMT device will introduce additional parasitic capacitances, the working state and device characteristics of the AlGaN/GaN HEMT device can be reflected more accurately, and the accuracy of the device model is improved.
    Type: Application
    Filed: December 25, 2017
    Publication date: November 14, 2019
    Inventors: Guangsheng WU, Haifeng ZHOU, Ging DiNG, Xiaocong LI, Jiaila WANG
  • Publication number: 20190322433
    Abstract: In the context of e-commerce, the packaging system of the present invention provides the necessary protection of consumer goods from rigors of transportation and parcel delivery while providing significant environment and cost savings.
    Type: Application
    Filed: March 15, 2019
    Publication date: October 24, 2019
    Inventors: Haifeng Zhou, Wanmin Yang
  • Publication number: 20190267472
    Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Runling Li, Haifeng Zhou
  • Patent number: 10332979
    Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 25, 2019
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Runling Li, Haifeng Zhou
  • Patent number: 10276450
    Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: April 30, 2019
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Tong Lei, Yongyue Chen, Haifeng Zhou
  • Patent number: 10177049
    Abstract: Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 8, 2019
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Haifeng Zhou, Jun Tan
  • Publication number: 20180240718
    Abstract: Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.
    Type: Application
    Filed: March 28, 2018
    Publication date: August 23, 2018
    Inventors: Haifeng ZHOU, Jun Tan
  • Patent number: 10008420
    Abstract: Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: June 26, 2018
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Haifeng Zhou, Jun Tan
  • Publication number: 20180174924
    Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.
    Type: Application
    Filed: February 10, 2017
    Publication date: June 21, 2018
    Applicant: Shanghai Huali Microelectronics Corporation
    Inventors: Tong Lei, Yongyue Chen, Haifeng Zhou