Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate, and a driving circuit layer and a light-emitting device layer on the base substrate. The display substrate includes a light-transmitting display area and a normal display area, the normal display area surrounds at least a portion of the light-transmitting display area. The normal display area includes multiple normal driving circuits and multiple dummy driving circuits; some dummy driving circuit are used for driving light-emitting devices located in the light-transmitting display area. The display substrate further includes multiple normal data lines coupled to the normal driving circuits; at least one normal data line is coupled to a data signal input terminal through a data lead; an orthographic projection of the data lead onto the base substrate at least partially overlaps an orthographic projection of the dummy driving circuit onto the base substrate.

Abstract: A display panel having a bonding region for bonding an integrated circuit is provided. The display panel includes a base substrate; and a plurality of bonding pin structures on the base substrate arranged in a plurality of columns, respectively. A respective bonding pin structure includes a respective bonding pin and connection lines on two ends of the respective bonding pin, respectively. Bonding pins of the plurality of bonding pin structures are arranged in N rows, N is a positive integer equal to or greater than 4. (N?1) number of connection lines pass through a region between two adjacent bonding pins arranged in a same row.

Abstract: A display substrate includes a substrate (100), a plurality of first pixel circuits (11), a plurality of second pixel circuits (12), a plurality of first light emitting elements (13), a plurality of second light emitting elements (14), at least one first reset control line (RST1), at least one first data line (51) and at least one first shielding wire (61). The first data line (51) at least includes a first sub-data line (511), a second sub-data line (512), and a first data transfer line (514) connecting the first sub-data line (511) and the second sub-data line (512). In a direction perpendicular to the display substrate, a first shielding wire (61) is located between a first reset control line (RST1) and a first data transfer line (514).

Abstract: Provided is a display panel including: a substrate, including a display region and a GOA region at least partially surrounding the display region; a plurality of pixels arranged in arrays, disposed in the display region; a first GOA circuit, disposed in the GOA region, wherein the first GOA circuit includes a plurality of cascaded first GOA units, each of the first GOA units being coupled to at least one row of the pixels and being configured to transmit a gate drive signal to the at least one row of the pixels; and a second GOA circuit, disposed in the GOA region, wherein the second GOA circuit includes a plurality of cascaded second GOA units, each of the second GOA units being coupled to at least one row of the pixels and being configured to transmit a light emission control signal to the at least one row of the pixels.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, multiple sub-pixels, multiple data lines, a test circuit, multiple data leads, at least one test pad, and at least one first test signal line. The multiple data lines are electrically connected to the multiple sub-pixels, and configured to provide data signals to the multiple sub-pixels. The multiple data leads are electrically connected to the multiple data lines and the test circuit. At least one test pad is located on at least one side of the test circuit. The at least one first test signal line is electrically connected to at least one test pad and the test circuit, and includes at least two conductive layers connected in parallel and electrically connected to each other.

Abstract: An array substrate is provided. The array substrate includes a voltage supply network. The voltage supply network includes, in a corner region of a peripheral area, a first peripheral voltage supply line; a plurality of second peripheral voltage supply lines; and an electrical connecting structure configured to connect the plurality of second peripheral voltage supply lines with the first peripheral voltage supply line. The electrical connecting structure crosses over at least one of the plurality of second peripheral voltage supply lines.

Abstract: A pixel circuit includes a driving sub-circuit coupled to a first node, a second node and a third node, a compensation sub-circuit coupled to the first node, the third node and a first scan signal terminal, an adjustment sub-circuit, and a writing sub-circuit. The compensation sub-circuit includes a first transistor group, and the first transistor group includes at least two first transistors connected in series. A fourth node is formed between a second electrode of a first first transistor and a first electrode of a second first transistor. The adjustment sub-circuit is coupled to the fourth node and at least one control terminal. The adjustment sub-circuit is configured to, in light-emitting phases, adjust a voltage of the fourth node under a control of a signal from the at least one control terminal, so as to reduce a voltage difference between the fourth node and the first node.

Abstract: A pixel driving circuit, including: a driving circuit, connected to a first node, a second node and a third node, and configured to input a driving current to the third node through the second node according to a signal of the first node; a compensation circuit, connected to the first node, the third node and a first gate driving signal end, and configured to turn on the first node and the third node in response to a signal of the first gate driving signal end; a first light-emitting control circuit, connected to the third node, a fourth node and a first enabling signal end, and configured to communicate with the third node and the fourth node in response to a signal of the first enabling signal end; a first reset circuit, connected to the fourth node, a first initial signal end and a first reset signal end, and configured to transmit a signal of the first initial signal end to the fourth node in response to a signal of the first reset signal end; and a second reset circuit, connected to the second node, a se

Abstract: A display substrate includes at least one scan driving circuit. The scan driving circuit includes a first voltage signal line, a second voltage signal line, a third voltage signal line, and shift registers. A shift register includes: first and second transistors disposed between the first voltage signal line and the second voltage signal line, third and fourth transistors disposed between the second voltage signal line and the third voltage signal line, at least one first scan signal line electrically connected to a first output terminal, and at least one second scan signal line electrically connected to a second output terminal. A second electrode of the first transistor and a second electrode of the second transistor are both electrically connected to the first output terminal; a second electrode of the third transistor and a second electrode of the fourth transistor are both electrically connected to a second output terminal.

Abstract: Provided are a display panel, a manufacturing method, and a display device. The display panel includes: a substrate including a display area and a peripheral area; a driving circuit layer including: a pixel circuit in the display area, and a gate driver circuit on a side of the pixel circuit in proximity to the peripheral area, and at least partially in the display area; a first metal layer on a side of the driving circuit layer away from the substrate, insulated from the driving circuit layer; and a first electrode layer in the display area and on a side of the first metal layer away from the substrate, insulated from the first metal layer, and electrically connected to the pixel circuit; where orthographic projections, on the substrate, of the first electrode layer, the first metal layer, and the gate driver circuit, are at least partially overlapped.

Abstract: Provided are a pixel circuit, display apparatus and driving method. The pixel circuit includes: a light-emitting device, a driving transistor configured to generate a driving current that drives the light-emitting device to emit light according to a data voltage, a light-emitting control circuit coupled with the driving transistor and configured to, in response to an effective level of a light-emitting control signal terminal, provide a driving current generated by the driving transistor to the light-emitting device, and drive the light-emitting device to emit light; a data-writing circuit coupled with a first electrode of the driving transistor and configured to operate in response to a plurality of effective levels that occur at intervals between first scanning signal terminals; and a threshold compensation circuit coupled with the driving transistor.

Abstract: A display panel and a display device are provided. The display panel includes: a display region; a peripheral region surrounding the display region; a plurality of pixel units, located in the display region and configured to display an image; a plurality of data lines, electrically connected with the plurality of pixel units and configured to input data signals to the plurality of pixel units; a plurality of data transmission lines, located in the peripheral region and connected with the plurality of data lines; and at least two repair structures, wherein each of the at least two repair structures includes a first repair line and a second repair line, the first repair line is overlapped with the plurality of data transmission lines, and the second repair line is overlapped with the plurality of data lines.

Abstract: Embodiments of this disclosure provide a display substrate and a display device. The display substrate includes: sub-pixels located on a base substrate; a first conductive layer located on one side of the base substrate, and including signal lines sequentially disposed in a first direction and extending towards a second direction, and signal line bulges and anode adaptor parts located on the same side of the signal line and disposed alternately; and anodes located between the first conductive layer and a pixel defining layer. Each anode includes an effective part exposed by a corresponding sub-pixel opening, the effective parts of at least part of the sub-pixels have overlapping regions with the signal line bulges and the anode adaptor parts in the second direction, and the second direction is perpendicular to the first direction.

Abstract: A display panel is disclosed. The display panel includes a base substrate; and an active layer arranged on a side of the base substrate. The active layer includes: a sixth active portion, a seventh active portion, a tenth active portion and a second initialization signal line, the second initialization signal line is connected to an end of the seventh active portion away from the sixth active portion, the second initialization signal line is used for providing an initialization signal to a seventh transistor, the seventh transistor comprises the seventh active portion, and the second initialization signal line extends along a first direction.

Abstract: An array substrate is provided. The array substrate includes a plurality of first subpixels in a first region and a plurality of second subpixels in a second region. The plurality of first subpixels include a plurality of first pixel driving circuits. The plurality of second subpixels include a plurality of second pixel driving circuits. A respective first pixel driving circuit of the plurality of first pixel driving circuits includes a smaller number of transistors than a respective second pixel driving circuit of the plurality of second pixel driving circuits. The first region has a light transmittance higher than the second region, and a subpixel density same as the second region.

Abstract: A display substrate and a manufacturing method therefor, and a display device are provided. The display substrate includes a drive circuit layer disposed on a substrate, the drive circuit layer includes a plurality of circuit units, at least one circuit unit includes a pixel drive circuit, a first power supply line providing a power supply signal to the pixel drive circuit, a data signal line providing a data signal to the pixel drive circuit, and a data fan-out line connected with the data signal line; at least a portion of the first power supply line, the data signal line, and the data fan-out line extends along a second direction and is arranged at intervals along a first direction, at least a portion of the data fan-out line is disposed between the first power supply line and the data signal line, the first direction intersects with the second direction.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes sub-pixels, a pixel defining pattern, and a defining structure. The sub-pixel includes a light-emitting functional layer. The pixel defining pattern includes first openings and second openings, a portion in the defining structure exposed by the second opening is configured to isolate the light-emitting functional layer. The sub-pixels include a first sub-pixel and a second sub-pixel, a turn-on voltage of the first sub-pixel is higher than that of the second sub-pixel; the defining structure includes a first defining structure surrounding the second sub-pixel and a second defining structure surrounding the second sub-pixel; the first defining structure is not exposed by the second opening; or a proportion of the first defining structure exposed by the second opening is less than a proportion of the second defining structure exposed by the second opening.

Abstract: A shift register and a driving method thereof, a gate driving circuit, and a display device are provided. The shift register includes: an input circuit configured to input an input voltage to a first node under control of a first clock signal; a first control circuit configured to output a first control signal to a first output node under control of the first clock signal, a voltage of the first node, and a second clock signal; a second control circuit configured to output a second control signal to the second output node under control of the voltage of the first node; and an output circuit configured to write a first voltage signal or a second voltage signal into a first output terminal as a first output signal under control of the first control signal and the second control signal.

Abstract: Provided are a display substrate, a driving method thereof, and a display apparatus. The display substrate includes multiple sub-pixels, a sub-pixel includes a pixel drive circuit and a light emitting device, the pixel drive circuit includes an initial signal line (INIT), a reset signal line (Reset) and multiple transistors, the initial signal line includes a first branch (INIT-1). Multiple transistors include a drive transistor, a first reset transistor and a second reset transistor, the drive transistor provides a drive current to the light emitting device, the first reset transistor resets a gate of the drive transistor through the INIT-1 under control of the reset signal line. The second reset transistor resets a first terminal of the light emitting device through the INIT-1 under control of the reset signal line. The first reset transistor and the second reset transistor in a same sub-pixel are controlled by a same reset signal line.

Abstract: A display substrate, and a display apparatus corresponding thereto and a manufacturing method therefor. The display substrate comprises: a display region and a non-display region, wherein the non-display region is provided with a gate driving circuit, which comprises a plurality of cascaded shift register units. Each shift register unit comprises: an input circuit (10), a first control circuit (11), a second control circuit (12) and an output circuit (15), wherein the first control circuit (11) is located between the input circuit (10) and the output circuit (15) in a first direction, and the first control circuit (11) is arranged in the first direction; and the second control circuit (12) is adjacent to the first control circuit (11) in a second direction; the first direction intersects with the second direction.