Abstract: The present disclosure provides a shift register including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and an impedance transistor; the second transistor has a first electrode coupled to a second node; the third transistor has a first electrode coupled to a first power terminal and a second electrode coupled to the second node; the fifth transistor has a control electrode coupled to a third node; the impedance transistor has a control electrode coupled to the first power terminal, a first electrode coupled to the second node, and a second electrode coupled to the third node.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, and includes a shift register unit, a first clock signal line, and a second clock signal line in a peripheral region; a first portion and a second portion of a first connection wire of the display substrate are connected to a first gate electrode of a first control transistor of the shift register unit; an orthographic projection of the first portion on the base substrate is on a side of an orthographic projection of an active layer of the first control transistor on the base substrate away from a display region; and an orthographic projection of the second portion on the base substrate is on a side of the orthographic projection of the active layer of the first control transistor on the base substrate close to the display region.

Abstract: Provided is a display substrate. A base substrate includes a display region (100), a binding region located on one side of the display region (100), and a first peripheral region (200) located between the display region and the binding region. The display region (100) comprises multiple display units. A power line (210, 220) is disposed in the first peripheral region (200) of the base substrate, and is electrically connected to the display units. An organic insulating layer is disposed on the side of the power line away from the base substrate. In the first peripheral region (200), the organic insulating layer includes at least two organic grooves and an isolation dam (410, 420) disposed between every two adjacent organic grooves, and the organic grooves penetrate through the organic insulating layer.

Abstract: A display substrate includes: a base substrate, a plurality of sub-pixels arranged on the base substrate, a plurality of gate lines, and a plurality of first compensation gate patterns; the sub-pixel includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes a compensation transistor; the compensation transistor includes a second compensation gate pattern, the first compensation gate pattern is located between a corresponding second compensation gate pattern and the base substrate, the first compensation gate pattern is coupled to a DC signal output terminal, and the second compensation gate pattern is coupled to a corresponding gate line; the compensation transistor includes a compensation active layer, the compensation active layer is located between the first compensation gate pattern and the second compensation gate pattern, and the compensation active layer includes a compensation channel portion.

Abstract: A display substrate, a manufacturing method and a display device are provided. At least one of the plurality of shift register units in the scan driving circuit includes an output circuit including an output transistor and an output reset transistor; a length of the active layer of the output transistor/the output reset transistor in the first direction is a first length/a second length, and a sum thereof is an output active length; a smaller one of minimum width of the active layer of the output transistor and the output reset transistor in a second direction is a first output active width, the first direction intersects the second direction; a ratio of the output active length to the first output active width is within a first predetermined ratio range greater than or equal to 3 and less than or equal to 11.

Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, a display panel, and an electronic apparatus. The array substrate includes: a base substrate; a light emitting layer on the base substrate; and a first electrode on a side of the light emitting layer away from the base substrate. The array substrate includes a light emitting area and a non-light emitting area, the first electrode is in the light emitting area and the non-light emitting area, and a thickness of a portion of the first electrode in the light emitting area is less than a thickness of a portion of the first electrode in the non-light emitting area.

Abstract: A display substrate and a display device are provided. Sub-pixels in the display substrate include a first electrode, a light emitting layer and a second electrode which are sequentially stacked; each second electrode includes a main body electrode and a connecting electrode. The sub-pixels include first color sub-pixels and second color sub-pixels, the main body electrode of a same first color sub-pixel is a continuous electrode. The sub-pixels include sub-pixel pairs, each sub-pixel pair includes a first pixel block and a second pixel block, a shape of the second electrode of the second pixel block is different from that of the second electrode of the first pixel block.

Abstract: A display substrate, a method of manufacturing the same, and a display apparatus are provided. Multiple subpixels in the display substrate include first and second subpixels. Each subpixel includes a power signal line pattern and a light-emitting element. The power signal line pattern includes first and second power line portions. At least a part of the first power line portion extends in a second direction. The light-emitting element includes an anode pattern. In the display substrate, an overlap between the anode pattern of the first subpixel and the power signal line pattern is larger in area than an overlap between the anode pattern of the second subpixel and the power signal line pattern, an overlap between the anode pattern of the first subpixel and the first power line portion is larger in area than an overlap between the anode pattern of the first subpixel and the second power line portion.

Abstract: A shift register includes: an input circuit configured to transmit an input signal received at an input signal terminal to a first node under control of a first clock signal transmitted by a first clock signal terminal; an output circuit configured to transmit a second clock signal received at a second clock signal terminal to an output signal terminal under control of a voltage of the first node; a first control circuit configured to, according to one of the second clock signal and a first voltage signal transmitted by a first voltage signal terminal, control a voltage of a second node under control of the voltage of the first node and the second clock signal; and a holding circuit configured to transmit the first voltage signal to the output signal terminal under control of the voltage of the second node.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, at least one group of contact pads, a plurality of first light-emitting elements, a plurality of first pixel driving circuits, a plurality of connecting traces, a plurality of data lines and a plurality of leads. The display area includes a first display area and a second display area; the first light-emitting elements are located in the first display area; the first pixel driving circuits are located in the second display area; the leads are located in the first display area and the peripheral area, and connect the data lines and the at least one group of contact pads; orthographic projections of the first light-emitting elements on a substrate surface of the base substrate are at least partly overlapped with orthographic projections of the leads on the substrate surface of the base substrate.

Abstract: A display substrate, a method for manufacturing the display substrate, and a display device. In the display substrate, the first sub-pixel and the second sub-pixel each include: a power signal line pattern, at least part of the power signal line pattern extends along the second direction; and a power compensation pattern, at least part of the power compensation pattern extends along the first direction, the power signal line pattern and the power compensation pattern are both located on a side of the first data line pattern and the second data line pattern close to the substrate; the power compensation pattern is electrically connected to the power signal line pattern and a power signal line pattern in an adjacent sub-pixel along the first direction.

Abstract: A display substrate, and a display apparatus corresponding thereto and a manufacturing method therefor. The display substrate comprises: a display region and a non-display region, wherein the non-display region is provided with a gate driving circuit, which comprises a plurality of cascaded shift register units. Each shift register unit comprises: an input circuit (10), a first control circuit (11), a second control circuit (12) and an output circuit (15), wherein the first control circuit (11) is located between the input circuit (10) and the output circuit (15) in a first direction, and the first control circuit (11) is arranged in the first direction; and the second control circuit (12) is adjacent to the first control circuit (11) in a second direction; the first direction intersects with the second direction.

Abstract: A display panel, a driving method, and a display device. The display panel includes: a base substrate, subpixels, driving lines, data lines, a gate driving circuit including clock signal lines and shift register units arranged in extension direction of clock signal lines. The clock signal lines is divided into clock signal line groups; the shift register units is divided into register unit groups; the shift register units in same register unit group are cascaded, adjacent two of shift register units in the extension direction are in different register unit groups; one register unit group corresponds to one clock signal line group; the gate of an input transistor is connected to a clock signal line in a corresponding clock signal line group, the second pole of input transistor is connected to the gate of an output transistor; the second pole of output transistor is connected to at least one driving line.

Abstract: Disclosed is a pixel circuit arranged in a display substrate, which comprises a first driving mode and a second driving mode. Content displayed in the display substrate comprises multiple display frames. In the first driving mode and the second driving mode, the display frames comprise refresh frames. A signal of a second scanning line is the same as that of a third scanning line. The time of which the signal of the second scanning line is an active level signal comprises a first refresh time period, a second refresh time period and a third refresh time period, which sequentially occur at intervals. During the second refresh time period, a signal of a first scanning line is an inactive level signal. The voltage of a signal at a reset voltage end is a positive voltage, and the voltage of a signal at a first initial voltage end is a negative voltage.

Abstract: According to a pixel circuit and a driving method therefor, and a display apparatus provided by the embodiments of the present disclosure, a signal of a data signal end may be provided to a first end of a driving transistor through a data writing circuit under the control of a signal of a scanning signal end. A control end of the driving transistor is initialized through a second reset circuit according to a signal of an initializing signal end; and under the control of a signal of a light emitting control signal end, a first power end and the first end of the driving transistor are turned on through a light emitting control circuit, and a second end of the driving transistor and a light emitting device are turned on.

Abstract: A display apparatus and driving method therefor. The apparatus comprises light emitting element, pixel circuit, scan signal line, data signal line, initial signal line, light emission control line, first power source line, and first reset line to third reset line. The pixel circuit comprises: first reset sub-circuit configured to provide a signal of the initial signal line to a first node; node control sub-circuit configured to provide a signal of the data signal line to a second node, compensate for the first node until a voltage thereof satisfies a threshold condition, provide a signal of the second node to the third node; light emission control sub-circuit configured to provide a signal of the first power source line to the second node and a signal of the third node to light emitting element; second reset sub-circuit configured to provide a signal of the initial signal line to light emitting element.

Abstract: The present disclosure provides a display substrate, a manufacturing method and a display device. At least one of the plurality of shift register units in the scan driving circuit includes an output circuit including an output transistor and an output reset transistor; a length of the active layer of the output transistor/the output reset transistor in the first direction is a first length/a second length, and a sum thereof is an output active length; a smaller one of minimum width of the active layer of the output transistor and the output reset transistor in a second direction is a first output active width, the first direction intersects the second direction; a ratio of the output active length to the first output active width is within a first predetermined ratio range greater than or equal to 3 and less than or equal to 11.

Abstract: A shift register unit, a driving method, a driving circuit and a display device. The shift register unit includes a first node control circuit, a second node control circuit, an output node control circuit, an output circuit, a maintaining circuit, and a potential control circuit. The first node control circuit controls the potential of the first node, the second node control circuit controls the potential of the second node, the output node control circuit controls the connection between the output terminal and the first voltage terminal under the control of the potential of the output node, the potential control circuit control the potential of the control terminal of the maintaining circuit according to the second clock signal; the maintaining circuit controls the connection between the output terminal and the second voltage terminal under the control of a potential of the control terminal of the maintaining circuit.

Abstract: Provided is a display substrate having a polygonal encapsulation region with a plurality of edges and a periphery region surrounding the encapsulation region. The display substrate includes a base substrate, and a partition structure within the periphery region on a side of the base substrate. The partition structure includes a plurality of isolation dams, arranged at intervals along a direction away from the encapsulation region, outside each edge of the encapsulation region. The plurality of edges include a first edge and a second edge, and a plurality of first isolation dams outside the first edge are not in connection with, and have more dams than, a plurality of second isolation dams outside the second edge.

Abstract: A pixel circuit, a driving method for same, and a display apparatus are provided. The pixel circuit includes a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, an emitting element. The driving sub-circuit provides a driving current for a third node under control of signals of first and second nodes. The writing sub-circuit writes a signal of the data signal terminal into the second node under control of a signal of a second scanning signal terminal. The first reset sub-circuit writes an initial voltage signal of a first initial signal terminal into the third node under control of a first scanning signal terminal and a first emitting control signal terminal. The compensation sub-circuit writes the initial voltage signal of the third node into the first node under control of a third scanning signal terminal, compensates the first node under control of the third scanning signal terminal.