Abstract: A method is provided of forming a contact to a semiconductor structure. A current-conducting member is formed which extends horizontally over a first portion of a semiconductor device region but not over a second portion of such semiconductor device region. A first film is formed which extends over the second portion and only partially over the member to expose a contact portion of the member. A first contact via is formed in conductive communication with the contact portion. The first contact via has a silicide-containing region self-aligned to an area of the member contacted by the contact via. A second contact via is formed in conductive communication with the second portion, the second contact via extending through the first film.

Abstract: An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent to the channel region. A first stressed region having a first type of stress is provided to underlie the channel region, in which the first type of stress is either compressive type or tensile type. Second stressed regions having a second type of stress are provided to underlie the source and drain regions, in which the second type of stress is an opposite one of the compressive type or tensile type stress of the first stressed region.

Abstract: A semiconductor device is provided with a stressed channel region, where the stresses film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surround the channel region, and may apply stress from all sides of the channel. Consequently, the stress film better surrounds the channel region of the semiconductor device and can apply more stress in the channel region.

Abstract: Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited in/or on the semiconductor substrate. Subsequently a second spacer covering the surface of the first spacer, and a contact liner over at least the gate stack, the second spacer and the silicide, are formed. Then an interlayer dielectric over the contact liner is deposited. Next, a metal contact opening is formed to expose the contact liner over the silicide. Finally, the opening is extended through the contact liner to expose the silicide without exposing the substrate.

Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

Abstract: A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device substrate with little to no nitride on a portion of the gate stack. The nitride film may be preferentially deposited only on the silicon substrate in a non-conformal layer, where little to no nitride is deposited on the upper portions of the gate stack. The nitride film may also be uniformly deposited on the silicon substrate and gate stack in a conformal layer, with the nitride film proximate the upper regions of the gate stack preferentially removed in a later step. In some embodiments, nitride near the top of the gate stack is removed by removing the upper portion of the gate stack. In any of the methods, stress in the transistor channel is enhanced by minimizing nitride deposited on the gate stack, while having nitride deposited on the substrate.

Abstract: A structure is provided in which a semiconductor device region has a first portion and a second portion, and a device disposed in the first and second portions. A current conducting member extends horizontally over the first portion but not over the second portion. A dielectric region, having a substantially planar upper surface, is disposed over the member, the dielectric region overlying substantially all of an area of the semiconductor device region that is occupied by the device. A dielectric barrier layer overlies the upper surface of the dielectric region, over substantially all of the area that is occupied by the device. The barrier layer is adapted to substantially prevent diffusion of one or more materials from above the barrier layer into the dielectric region. A contact via extends through the barrier layer and the dielectric region, the contact via in conductive communication with at least one of the member and the second portion of the semiconductor device region.

Abstract: A structure is provided which includes a semiconductor device region including a first portion and a second portion. A current-conducting member is provided, which extends horizontally over the first portion but not over the second portion. A first film, such as a stress-imparting film, extends over the second portion and only partially over the current-conducting member to expose a contact portion of the member. A first contact via is provided in conductive communication with the contact portion of the member, the first contact via having a self-aligned silicide-containing region. A second contact via is provided in conductive communication with the second portion of the semiconductor device region, the second contact via extending through the first film.

Abstract: An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation within source and drain regions within the substrate at the base of the transistor gate stack. The liner also covers a resistor gate stack preventing silicide formation within or adjacent to the resistor gate stack.

Abstract: The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

Abstract: An SRAM in a CMOS integrated circuit is subjected to stress on the channels of its transistors; compressive stress on the pull-up and pass gate transistors and tensile stress on the pull-down transistors in a version designed to improve stability; and compressive stress on the pull-up transistors and tensile stress on the pull-down and pass gate transistors in a version designed to reduce the cell size and increase speed of operation.

Abstract: Disclosed is a method of forming an integrated circuit structure having first-type transistors, such as P-type field effect transistors (PFETs) and complementary second-type transistors, such as N-type field effect transistors (NFETs) on the same substrate. More specifically, the invention forms gate conductors above channel regions in the substrate, sidewall spacers adjacent the gate conductors, and source and drain extensions in the substrate. The sidewall spacers are larger (extend further from the gate conductor) in the PFETs than in the NFETs. The sidewall spacers align the source and drain extensions during the implanting process. Therefore, the larger sidewall spacers position (align) the source and drain implants further from the channel region for the PFETs when compared to the NFETs. Then, during the subsequent annealing processes, the faster moving PFET impurities will be restrained from diffusing too far into the channel region under the gate conductor.

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

Abstract: A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.

Abstract: A electrostatic adhesion tester for thin film conductors. In one embodiment, a device is provided for testing the adhesion strength of a thin film conductor that has been formed upon a substrate. The device includes an adhesion tester that is primarily comprised of a conducting portion. The conducting portion is applied to the thin film conductor so that it does not physically contact the thin film conductor, but leaves a small space there between. A power supply may further be provided for coupling to either the adhesion tester, the thin film conductor, or both in order to create a potential difference between the conducting portion and the thin film conductor. The potential difference creates an electric field between the conducting portion and the thin film conductor that induces stress in the thin film conductor.