Abstract: Aspects disclosed include a semiconductor die including a conductive bridge comprising a metal via coupling two adjacent metal interconnects in a single metal layer to address tiger tooth defects. The die includes a first dielectric layer in which the two adjacent metal interconnects are formed. The metal via is coupled to the top surface of the two adjacent metal interconnects and extends over the top surface of the first dielectric layer between the two adjacent metal interconnects. The conductive bridge includes a portion of the two adjacent metal interconnects coupled to the bottom surface of the metal via and a dielectric protection layer between the bottom surface of the metal via and the top surface of the first dielectric layer and co-extensive with the bottom surface of the metal via. The two adjacent metal interconnects do not have any intervening metal interconnects between them.

Abstract: A fin field effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate and extending through the STI region. The FinFET further includes a second fin structure on the substrate and extending through the STI region. The FinFET also includes a metal gate on the STI region, on the first fin structure, and on the second fin structure. The metal gate is composed of a first sub-metal gate cut line filled with a first stressor material, and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

Abstract: A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.

Abstract: Aspects disclosed include a semiconductor die including a transistor coupled to a contact layer wherein the contact layer includes a metal contact having a sidewall with a reduced height to promote connectivity with an adjacent via. The die comprises the contact layer adjacent to an epitaxial layer of the transistor. The contact layer comprises a metal contact adjacent to the epitaxial layer and having a first height. The metal contact comprises a plurality of sidewalls wherein at least one of the plurality of sidewalls has a second height which is less than the first height resulting in increased metal at a surface of the metal contact. The die further comprising a via layer adjacent to the contact layer. The via layer comprising a via adjacent to the surface of the metal contact increasing the connectivity between the via and the metal contact.

Abstract: Disclosed are apparatuses including transistor and methods for fabricating the same. The transistor may include a drain substantially enclosed in a drain silicide layer, wherein an integral drain via portion of the drain silicide layer is coupled to a second drain contact and wherein a first drain via couples the drain silicide layer to a first drain contact. The transistor may include a source substantially enclosed in a source silicide layer, wherein an integral source via portion of the source silicide layer is coupled to a second source contact and wherein a first source via couples the source silicide layer to a first source contact. The transistor may include a gate disposed between the source and the drain.

Abstract: A field effect transistor (FET) is described. The FET includes a substrate, having a first vertical structure on the substrate, including a source/drain region having a first stressor material. The FET also includes a second vertical structure on the substrate and including a drain/source region having a second stressor material different from the first stressor material. The FET further includes a metal gate on the first vertical structure and on the second vertical structure.

Abstract: Aspects disclosed include a semiconductor die including a transistor coupled to a contact layer wherein the contact layer includes a metal contact having a sidewall with a reduced height to promote connectivity with an adjacent via. The die comprises the contact layer adjacent to an epitaxial layer of the transistor. The contact layer comprises a metal contact adjacent to the epitaxial layer and having a first height. The metal contact comprises a plurality of sidewalls wherein at least one of the plurality of sidewalls has a second height which is less than the first height resulting in increased metal at a surface of the metal contact. The die further comprising a via layer adjacent to the contact layer. The via layer comprising a via adjacent to the surface of the metal contact increasing the connectivity between the via and the metal contact.

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a first gate structure disposed on a substrate and having a first channel length; a second gate structure disposed on the substrate and having the first channel length, a first source/drain space between the first gate structure and the second gate structure having a first distance; a third gate structure disposed on the substrate and having a second channel length; and a fourth gate structure disposed on the substrate and having the second channel length, a second source/drain space between the third gate structure and the fourth gate structure having a second distance. In an aspect, the second distance ranges from 0.75 times to 1.25 times the first distance.

Abstract: A method and device for establishing a spectrum. The device comprises a light source, a micro-nano filter device and a voltage control apparatus; the micro-nano filter device comprises a cover plate and a substrate which is provided with a conductive electrode, a film layer and an electrically controlled phase-change material being located between the substrate and the cover plate; the cover plate and the substrate layer are made of a transparent material, the transparent material having a flat surface, covering a conductive film which comprises an ITO layer, and serving as an electrode of an applied external voltage; nano-structure units arrayed periodically are prepared on the conductive film, the nano-structure units arrayed periodically being made of one of a metal material, a metal oxide material or a semiconductor material.

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate structure disposed on a substrate, a gate spacer adjacent to the gate structure, a source/drain structure adjacent to the gate spacer, a first dielectric layer disposed on the substrate and the source/drain structure, an etch stop spacer over the first dielectric layer and adjacent to the gate spacer, and an etch stop layer over the gate structure, the gate spacer, and the etch stop spacer. The semiconductor structure further includes a source/drain contact extending through the etch stop layer and the first dielectric layer and in contact with the source/drain structure, a sidewall of the source/drain contact adjoining a sidewall of the etch stop layer and a sidewall of the etch stop spacer.

Abstract: A multi-band, shared-aperture, circularly polarized phased array antenna relating to the field of antenna technology is disclosed. Specifically, two multi-band, shared-aperture, circularly polarized phased array antenna designs are disclosed. By integrating multiple circularly polarized endfire antennas with different operation bands into one aperture, a shared-aperture antenna array is achieved. The bandwidth and crossband port isolation of this antenna are enhanced, and the antenna also has the properties of miniaturization, feasibility, and ease of connection with circuits.

Abstract: Disclosed are devices that include a contact for electrical connection with a source/drain. The contact occupies a full width of a contact well other than areas occupied by sidewall spacers. As a result, high resistivity (due to the presence of liners and nucleation layers within the contact well in conventional devices) is reduced or eliminated.

Abstract: A gate-all-around (GAA) field effect transistor (FET) structure and method for making the same is disclosed. In an aspects, a GAA FET includes a gate structure, extending in a first horizontal direction and disposed between first and second source/drain (S/D) epitaxial (EPI) structures and having a vertical metal gate structure with a first portion containing a set of vertically-stacked, horizontal channels connecting the first and second EPI S/D structures through the vertical metal gate structure, and a second portion having no channels. The GAA FET also includes a metal gate recess stop structure extending in the first horizontal direction and disposed above the first portion of the vertical metal gate structure, and a frontside inter-layer dielectric (ILD) layer disposed above the vertical metal gate structure and the first metal gate recess stop structure.

Abstract: A gate all around (GAA) field effect transistor (GAA FET) is described. The GAA FET includes a substrate, having a nanosheet structure on the substrate. The GAA FET also includes a source/drain (SD) region in the substrate and coupled to a first end of the nanosheet structure. The GAA FET further includes a drain/source (DS) region in the substrate and coupled to a second end opposite the first end of the nanosheet structure. The GAA FET also includes a metal gate on the nanosheet structure to define channels between the source/drain region and the drain/source region. The GAA FET further includes a trench oxide blocking a bottom channel of the channels.

Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

Abstract: A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

Abstract: A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region to improve carrier mobility, thereby increasing drive strength. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region to further improve carrier mobility. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.

Abstract: A field effect transistor (FET) is described. The FET includes a substrate, having a first vertical structure on the substrate, including a source/drain region having a first stressor material. The FET also includes a second vertical structure on the substrate and including a drain/source region having a second stressor material different from the first stressor material. The FET further includes a metal gate on the first vertical structure and on the second vertical structure.

Abstract: Disclosed are devices that include a direct N/P local interconnect with minimal recess on shallow trench isolation (STI) oxide. This reduces undesirable coupling capacitance with active gate, which in turn improves AC performance of the device. Pull or even partial replacement of STI oxide with low-k dielectric can further reduce coupling capacitance.

Abstract: Gate-all-around (GAA) field-effect transistor (FET) device employing strain material structure in inactive gate region(s) of a gate for applying channel strain to the channel(s) of the GAA FET for increased carrier mobility. The GAA FET device includes a GAA P-type (P) FET (PFET) and a GAA N-type (N) FET (NFET) served by a gate with a strain material in the inactive gate region(s) of the gate adjacent to the active gates of the GAA NFET and GAA PFET. In this manner, the strain material applies strain to both the GAA NFET and GAA PFET channels in the elongated direction of the gate in a direction orthogonal to their channel directions between the respective sources and drains, so that a strain material of the same strain type can be used to increase carrier mobility of both the GAA NFET and GAA PFET alike.