Abstract: An integrated device that includes a substrate, a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled to only the gate.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with buried rails (e.g., buried power and ground rails). One example semiconductor device generally includes a substrate; a first rail, wherein a portion of the first rail is disposed in the substrate, the portion of the first rail having a first width greater than a second width of another portion of the first rail; a second rail, wherein a portion of the second rail is disposed in the substrate, the portion of the second rail having a third width greater than a fourth width of another portion of the second rail; and one or more transistors disposed above the substrate and between the first rail and the second rail.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a buried power rail (BPR) having decreased resistance and a method of fabricating such a semiconductor device with a BPR. An example semiconductor device generally includes a substrate, a first transistor structure disposed above the substrate, a second transistor structure disposed above the substrate, and a BPR structure disposed between the first transistor structure and the second transistor structure. The BPR structure generally includes at least two distinguishable portions, which may be a first portion disposed above a second portion, the second portion having a greater width than the first portion.

Abstract: A transistor channel profile structure may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include different fin profiles for the NMOS transistors and the PMOS transistors, such as the NMOS fins are thicker than the PMOS fins or the NMOS fin has a straight vertical surface and the PMOS fin has a notch at a fin bottom region. In still another example, a transistor circuit may include different nano-sheet profiles for a NMOS GAA device and a PMOS GAA device where the NMOS nano-sheet is thicker than the PMOS nano-sheet. Such configurations optimize the NMOS and the PMOS transistors with the NMOS having a low channel resistance while the PMOS has a lower short channel effect.

Abstract: Disclosed are examples of 3D metal-insulator-metal (MIM) capacitor structures, e.g., in semiconductor packages. The disclosed 3D MIM capacitors provide high capacitance in small areas. As such, the disclosed 3D MIM capacitors may be used as decoupling capacities for high performance computing (HPC) processors.

Abstract: To prevent short defects between source/drains of transistors of a complementary cell circuit, isolation walls are formed in an isolation region between the source/drains of the transistors prior to growing a P-type epitaxial layer and an N-type epitaxial layer on respective sides of the isolation region. The isolation walls provide a physical barrier to prevent formation of short defects that can otherwise form between the P-type and N-type epitaxial layers. Thus, the isolation walls prevent circuit failures resulting from electrical shorts between source/drain regions of transistors in complementary cell circuits. A width of the isolation region between a P-type transistor and an N-type transistor in a circuit cell layout can be reduced so that a total layout area of the complementary cell circuit can be reduced without reducing product yield. A gate cut may be formed in the dummy gate with a process of forming the isolation walls.

Abstract: Methods, systems, and devices for double side back-end-of-line (BEOL) metallization for pseudo through-silicon via (pTSV) integration are described. An integrated circuit (IC) may include multiple metallic layers integrated within multiple layers of a multi-dimensional integrated stack (e.g., a three dimensional (3D) integrated stack). By performing a BEOL metallization process, the integrated circuit may implement techniques for 3D vertical chip integration. For example, a first set of layers may be formed during a first portion of a BEOL process and a second portion of the BEOL process may integrate a second set of metallic layers as well as a buried power delivery network (PDN). The metallic layers may form a number of pTSVs and may promote a PDN to experience a reduced PDN IR drop. The PDN may be integrated and the pTSVs may be formed by integrating the metallic layers within a number of dielectric layers.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with buried rails (e.g., buried power and ground rails). One example semiconductor device generally includes a substrate; a first rail, wherein a portion of the first rail is disposed in the substrate, the portion of the first rail having a first width greater than a second width of another portion of the first rail; a second rail, wherein a portion of the second rail is disposed in the substrate, the portion of the second rail having a third width greater than a fourth width of another portion of the second rail; and one or more transistors disposed above the substrate and between the first rail and the second rail.

Abstract: A semiconductor device comprising an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor and a P-type metal oxide semiconductor (PMOS) GAA transistor with high charge mobility channel materials is disclosed. The semiconductor device may include a substrate. The semiconductor device may also include an NMOS GAA transistor on the substrate, wherein the NMOS GAA transistor comprises a first channel material. The semiconductor device may further include a PMOS GAA transistor on the substrate, wherein the PMOS GAA transistor comprises a second channel material. The first channel material may have an electron mobility greater than an electron mobility of Silicon (Si) and the second channel material may have a hole mobility greater than a hole mobility of Si.

Abstract: A transistor channel profile structure may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include different fin profiles for the NMOS transistors and the PMOS transistors, such as the NMOS fins are thicker than the PMOS fins or the NMOS fin has a straight vertical surface and the PMOS fin has a notch at a fin bottom region. In still another example, a transistor circuit may include different nano-sheet profiles for a NMOS GAA device and a PMOS GAA device where the NMOS nano-sheet is thicker than the PMOS nano-sheet. Such configurations optimize the NMOS and the PMOS transistors with the NMOS having a low channel resistance while the PMOS has a lower short channel effect.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a heterojunction bipolar transistor (HBT) integrated with a gate-all-around (GAA) transistor. One example semiconductor device generally includes a first substrate, a second substrate adjacent to the first substrate, a GAA transistor disposed above the first substrate, and a HBT disposed above the second substrate. Other aspects of the present disclosure generally relate to a method for fabricating a semiconductor device. An exemplary fabrication method generally comprises forming a GAA transistor disposed above a first substrate and forming a HBT disposed above a second substrate, wherein the second substrate is adjacent to the first substrate.

Abstract: A gate-all-around (GAA) transistor has an insulator on a substrate. The GAA transistor also may have different crystalline structures for P-type work material and N-type work material. The GAA transistor includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate section and a substrate, an insulator is added on the substrate. Further improvements are made in performance of a circuit having both P-type work material and N-type work material by providing different crystalline lattice structures for the work material.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having an insulator region disposed on at least one edge of a semiconductor fin structure. An example semiconductor device generally includes a first semiconductor region, an insulator region, a double diffusion break, and a first gate region. The first semiconductor region comprises a first fin structure and a second fin structure separated by a cavity. The insulator region is disposed along an edge of the first fin structure. The double diffusion break is disposed adjacent to the insulator region in the cavity. The first gate region is disposed around a portion of the first fin structure.

Abstract: A gate all around transistor may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include a dielectric or air gap as an insulator between the channels of the transistors in the circuit. In another example, a transistor may include a first channel surrounded by a first metal, a second channel surrounded by a second metal proximate to the first channel, and an insulator, such as a dielectric or air gap, between the first metal and the second metal. The insulator helps reduce the parasitic capacitance between the source/drain regions and the metal fill regions of the transistor.

Abstract: The parasitic capacitance of a transistor may be reduced by mismatching the source and drain. Faster low finger count transistors may be achieved with lower drain capacitance and a frequency gain on the D1 inverter as described for the examples herein. In one such example, a transistor includes a source and a drain wherein a length of the source is more than a length of the drain, a width of the source is more than a width of the drain, or a height of the source is more than a height of the drain.

Abstract: A semiconductor device with low parasitic capacitance comprises a substrate. The semiconductor device also comprises a gate region on the substrate. The semiconductor device further comprises a contact region on the substrate, wherein the contact region comprises a first portion and a second portion, wherein the first portion is in contact with the substrate and has a first surface above the substrate, and wherein the second portion is in contact with the substrate and has a second surface above the substrate different from the first surface.

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a ferroelectric (FE) semiconductor device having a channel region; a gate oxide; a FE region, wherein the gate oxide is disposed between the FE region and the channel region; a gate region, wherein the FE region is disposed between the gate oxide and the gate region; a first semiconductor region disposed adjacent to the channel region; and a second semiconductor region disposed adjacent to the channel region. The semiconductor device may also include a transistor, wherein a region of the transistor is connected to the gate region, the first semiconductor region, or the second semiconductor region of the FE semiconductor device.

Abstract: An integrated device that includes a substrate, a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled to only the gate.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a gate-cut isolation structure. An example method of fabricating semiconductor device generally includes forming a dielectric region between a first semiconductor region and a second semiconductor region. The method also includes forming a first gate region disposed above and spanning a width of the dielectric region between the first and second semiconductor regions, wherein the first gate region is also disposed above at least a portion of the first semiconductor region and above at least a portion of the second semiconductor region. The method further includes concurrently forming an SDB and a gate-cut isolation structure, wherein the SDB intersects the first and second semiconductor regions and wherein the gate-cut isolation structure electrically separates the first gate region into a first portion associated with the first semiconductor region and a second portion associated with the second semiconductor region.

Abstract: A gate all around transistor may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include a dielectric or air gap as an insulator between the channels of the transistors in the circuit. In another example, a transistor may include a first channel surrounded by a first metal, a second channel surrounded by a second metal proximate to the first channel, and an insulator, such as a dielectric or air gap, between the first metal and the second metal. The insulator helps reduce the parasitic capacitance between the source/drain regions and the metal fill regions of the transistor.