Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, and a display apparatus. The array substrate includes a plurality of gate lines (20) and a plurality of data lines (50) disposed on a base substrate (11), the plurality of gate lines (20) extend along a first direction, the plurality of data lines (50) extend in a second direction, the plurality of gate lines (20) and the plurality of data lines (50) are intersected to define a plurality of sub-pixels, the sub-pixel includes a thin film transistor (10), a pixel electrode (80) and a common electrode (90), the common electrode (90) in one sub-pixel is connected with the common electrode (90) in the adjacent sub-pixel through a common connection portion (110).

Abstract: Provided are a display substrate and a display device. The first display region includes at least two domains spaced apart in the first direction and a first space between the at least two domains, the second display region includes at least two domains spaced apart in the first direction and a second space located between the at least two domains of the second display region; each pixel units further includes a discharge line and a common electrode strip, the discharge line includes a first conductive part and a second conductive part, the first conductive part is at the first space, the second conductive part is at the second space, the common electrode strip is at an edge of the first display region adjacent to the data lines, and no common electrode strip is arranged on an edge of the second display region adjacent to the data lines.

Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, and a display apparatus. The array substrate includes a plurality of gate lines (20) and a plurality of data lines (50) disposed on a base substrate (11), the plurality of gate lines (20) extend along a first direction, the plurality of data lines (50) extend in a second direction, the plurality of gate lines (20) and the plurality of data lines (50) are intersected to define a plurality of sub-pixels, the sub-pixel includes a thin film transistor (10), a pixel electrode (80) and a common electrode (90), the common electrode (90) in one sub-pixel is connected with the common electrode (90) in the adjacent sub-pixel through a common connection portion (110).

Abstract: An array substrate and a display panel are described. The array substrate may include a first base; a plurality of pixel units arrayed on the first base in a row direction and a column direction; each of the pixel units comprising at least two sub-pixels arranged in the row direction; a plurality of first scanning lines sequentially arranged on the first base in the column direction, at least one first scanning line being arranged at a side of each row of pixel units in the column direction, the first scanning lines being connected with the sub-pixels; and a plurality of second scanning lines sequentially arranged on the first base in the row direction, at least one second scanning line being arranged at a side of each column of pixel units in the row direction.

Abstract: Provided is an array substrate. The array substrate includes: a base substrate; a plurality of clock lines; a plurality of clock leads; a plurality of shift register units; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate.

Abstract: A thin film transistor, an array substrate and a display device are provided. The thin film transistor is on a base substrate and includes a gate electrode, a first electrode, and a second electrode on the base substrate. The gate electrode includes a first body portion and a first extension portion extending along the first direction, electrically connected with the first body portion, and spaced apart from the first body portion by a first spacing.

Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Abstract: An Embodiment of the present disclosure provide a display substrate, including a base substrate, and a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of common electrodes and a plurality of pixel electrodes on the base substrate. The second scanning lines are parallel to the data lines, and the second scanning lines, the common electrodes and the pixel electrodes are in different layers. The common electrodes are located on a side of the second scanning lines and the data lines away from the base substrate, and on a side of the pixel electrodes proximal to the base substrate. An orthographic projection of one of the data line and the second scanning line on the base substrate is located in a spacer region between adjacent pixel electrodes.

Abstract: A display panel includes: a first active area and at least one second active area, a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being in the first active area, and each of the sub-pixels including a common electrode; grid lines and data lines, at least one of the data lines being located at a junction of the first active area and the second active area; a plurality of first conductive patterns at least in the second active area, and the first conductive patterns being electrically connected to one of the grid lines or the common electrode; and a plurality of second conductive patterns in the second active area and electrically connected to the data line at the junction, orthographic projections of part first conductive patterns on the substrate overlap orthographic projections of the second conductive patterns on the substrate.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: The present disclosure relates to the field of display technologies and, in particular to a display panel and an electronic device. The display panel comprises: Q rows of first scanning line groups arranged sequentially along a column direction; M columns of second scanning line groups arranged sequentially along a row direction; and at least one gate drive circuit, located on a side of the Q-th row of the first scanning line groups away from the (Q?1)-th row of the first scanning line groups. Each gate drive circuit comprises Q columns of shift register unit groups cascaded in stages. The q-th stage of the shift register unit groups is connected with the q-th row of the first scanning line groups through at least one column of the second scanning line groups. M?Q>1, 1?q?Q, and M, N, Q, q are all positive integers.

Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, and a display apparatus. The array substrate includes a plurality of gate lines (20) and a plurality of data lines (50) disposed on a base substrate (11), the plurality of gate lines (20) extend along a first direction, the plurality of data lines (50) extend in a second direction, the plurality of gate lines (20) and the plurality of data lines (50) are intersected to define a plurality of sub-pixels, the sub-pixel includes a thin film transistor (10), a pixel electrode (80) and a common electrode (90), the common electrode (90) in one sub-pixel is connected with the common electrode (90) in the adjacent sub-pixel through a common connection portion (110).

Abstract: A light control panel, having a dimming area and a peripheral area surrounding the dimming area; wherein the light control panel includes a first substrate and a second substrate oppositely disposed, and a first liquid crystal layer therebetween; the first substrate includes a signal connecting line on the first base substrate; the signal connecting line includes a first signal sub-line and a second signal sub-line which are electrically connected together and in different layers; a connecting position between the first signal sub-line and the second signal sub-line is in the peripheral area; and the slot at a position corresponding to the connecting position between the first signal sub-line and the second signal sub-line is formed with a protrusion, and an orthographic projection of the slot on the first base substrate overlaps an orthographic projection of the first signal sub-line on the first base substrate.

Abstract: A display device, a gate drive circuit, a shift register and a control method are disclosed. The shift register includes a first shift register unit and a second shift register unit, the first shift register unit is configured to write a first control signal to the first node, and write a first clock signal to the first signal output terminal under control of a voltage of the first node; the second shift register unit is configured to write a second clock signal to the second signal output terminal under control of the voltage of the first node; during time of a frame, the first clock signal and a first input signal provided by a first signal input terminal are pulse signals, and the second clock signal is a DC signal.

Abstract: A light control panel includes a first substrate and a second substrate oppositely disposed, and a first liquid crystal layer therebetween; the first substrate includes: a first base substrate; and a signal transmission line on a side of the first base substrate close to the first liquid crystal layer and in the peripheral area, the second substrate includes: a second base substrate; and a first black matrix layer on a side of the second base substrate close to the first liquid crystal layer and in the dimming area and the peripheral area; the first black matrix layer has a slot in the peripheral area, and an orthographic projection of at least a part of the slot on the first base substrate is on a side of an orthographic projection of the signal transmission line on the first base substrate, close to the dimming area.

Abstract: Provided is an array substrate. The array substrate includes at least one pad group disposed in a peripheral region of a base substrate, wherein the at least one pad group includes a sector pad group in which the pads are distributed in a sector shape. Therefore, the bonding yield between the array substrate and the circuit board is increased.

Abstract: A display device and a manufacturing method thereof, an electronic device, and a light control panel are provided. The display device includes a light control panel and a display liquid crystal panel. The display liquid crystal panel is on a light-emitting side of the light control panel; the light control panel includes a light control region, and the light control region is configured to provide adjusted backlight to the display liquid crystal panel; the display liquid crystal panel includes a display region, and the display region is configured to receive the adjusted backlight to perform display; and a distance between two opposite edges of the light control region in at least one direction is greater than a distance between two opposite edges of the display region in the at least one direction.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: A display device and a manufacturing method thereof, an electronic device, and a light control panel are provided. The display device includes a light control panel and a display liquid crystal panel. The display liquid crystal panel is on a light-emitting side of the light control panel; the light control panel includes a light control region, and the light control region is configured to provide adjusted backlight to the display liquid crystal panel; the display liquid crystal panel includes a display region, and the display region is configured to receive the adjusted backlight to perform display; and a distance between two opposite edges of the light control region in at least one direction is greater than a distance between two opposite edges of the display region in the at least one direction.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.