Patents by Inventor Haipeng Yang

Haipeng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9773817
    Abstract: The present invention provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a gate electrode, an active layer, an etch stop layer, a source electrode and a drain electrode. The etch stop layer is provided between the active layer and the source and drain electrodes, a first via hole and a second via hole are formed in the etch stop layer, the source electrode is connected with the active layer through the first via hole, the drain electrode is connected with the active layer through the second via hole, and the gate electrode is overlapped with a part of the first via hole and a part of the second via hole respectively and is overlapped with a portion between the first via hole and the second via hole.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: September 26, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Haipeng Yang, Yongjun Yoon, Zhizhong Tu, Jaikwang Kim
  • Patent number: 9766520
    Abstract: The invention discloses array substrate, manufacturing method thereof, display panel and display device, array substrate comprises TFTs, common electrodes, common electrode lines, data lines and gate lines, each TFT comprises gate, active layer corresponding to the gate, protective layer corresponding to the gate line or gate, and ESL, the active layer and protective layer are provided in the same layer and separated from each other; the ESL is provided with source holes and drain hole corresponding to the active layer, protective hole corresponding to the protective layer but not overlapping with the data line, and connecting holes corresponding to the common electrode and common electrode line; and distance between each connecting hole and the protective hole closest thereto is smaller than that between the connecting hole and the source or drain hole closest thereto, and/or, diameter of said protective hole is smaller than those of the source and drain holes.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 19, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Wei Feng, Guangyan Tian, Haipeng Yang, Xuebing Jiang, Xiaoye Ma
  • Publication number: 20170199410
    Abstract: An array substrate, a method of manufacturing the same and a liquid crystal display panel are disclosed. In the array substrate, a connection part for connecting two adjacent pixel electrodes is configured to enclose the spacer from three sides and a corresponding thin film transistor is arranged to enclose the spacer from a side other than the three sides. A distance between an upper surface of the connection part and an upper surface of the base substrate is larger than a distance between a lower surface of the spacer and the upper surface of the base substrate. With this configuration, the spacer is limited within a position limiting structure formed by the connection part and the thin film transistor.
    Type: Application
    Filed: July 25, 2016
    Publication date: July 13, 2017
    Inventors: Peng Jiang, Haipeng Yang, Ke Dai, Yong Jun Yoon, Zhangtao Wang, Bingbing Yan
  • Publication number: 20170176789
    Abstract: An embodiment of the present disclosure relates to the field of display technology, especially to a peripheral wiring structure of a display substrate, and a display substrate.
    Type: Application
    Filed: June 8, 2015
    Publication date: June 22, 2017
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Weihua Jia, Peng Jiang, Haipeng Yang, Jaik-Wang Kim, Yong-Jun Yoon
  • Publication number: 20170148818
    Abstract: A pixel structure, a display panel and a manufacturing method of the pixel structure are disclosed. The pixel structure includes: gate lines extending in parallel in a first direction; data lines extending in parallel in a second direction; and a plurality of pixel units defined by the gate lines and the data lines. One of the data lines is disposed between two pixel units which are adjacent to each other in the first direction, and two of the gate lines are disposed between two pixel units which are adjacent to each other in the second direction. Each of the pixel units comprises two pixel regions which are arranged side by side in the first direction, each of the pixel regions comprises a pixel electrode, and each of the pixel units comprises a unitary common electrode which covers the two pixel regions.
    Type: Application
    Filed: October 16, 2015
    Publication date: May 25, 2017
    Applicants: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Weihua Jia, Haipeng Yang, Jaikwang Kim, Yongjun Yoon
  • Publication number: 20170139297
    Abstract: The present invention relates to a display substrate and a method for fabricating the same, a display panel and a display device. The display substrate comprises a plurality of pixels, each of which has a display region, a non-display region being between the plurality of pixels, and the display substrate further comprises a protection metal layer covering the non-display region. In the display substrate, the protection metal layer covers the non-display region of the display substrate so as to shield the structures of the thin-film transistors, signal lines and the like on the display substrate, and thus the stability of structure of the display panel as well as the high resolution of the display panel and excellent display effect thereof can be ensured, and, in the meantime, the procedure of fabrication process is simplified, the manufacture efficiency is improved, and the cost for manufacturing is reduced.
    Type: Application
    Filed: January 6, 2016
    Publication date: May 18, 2017
    Applicants: BOE Technology Group Co., Ltd.
    Inventors: Binbin CAO, Peng JIANG, Peng CHEN, Jongwon MOON, Yinhu HUANG, Chengshao YANG, Haipeng YANG
  • Publication number: 20170108745
    Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate includes a base substrate, a plurality of pixel units arranged in a matrix and a plurality of common electrode lines extending along the column direction on the base substrate. There are two scanning signal lines between two adjacent rows of pixel units, and pixel units in a (2N+1)-th column and a (2N+2)-th column are taken as one pixel unit group, N being selected from integers greater than or equal to zero. The respective common electrode lines are located between two adjacent pixel unit groups.
    Type: Application
    Filed: August 11, 2016
    Publication date: April 20, 2017
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD .
    Inventors: Weihua JIA, Peng JIANG, Haipeng YANG, Yong Jun YOON, Zhangtao WANG
  • Publication number: 20160349580
    Abstract: The invention discloses array substrate, manufacturing method thereof, display panel and display device, array substrate comprises TFTs, common electrodes, common electrode lines, data lines and gate lines, each TFT comprises gate, active layer corresponding to the gate, protective layer corresponding to the gate line or gate, and ESL, the active layer and protective layer are provided in the same layer and separated from each other; the ESL is provided with source holes and drain hole corresponding to the active layer, protective hole corresponding to the protective layer but not overlapping with the data line, and connecting holes corresponding to the common electrode and common electrode line; and distance between each connecting hole and the protective hole closest thereto is smaller than that between the connecting hole and the source or drain hole closest thereto, and/or, diameter of said protective hole is smaller than those of the source and drain holes.
    Type: Application
    Filed: March 18, 2015
    Publication date: December 1, 2016
    Inventors: Wei FENG, Guangyan TIAN, Haipeng YANG, Xuebing JIANG, Xiaoye MA
  • Publication number: 20160327841
    Abstract: A display panel and manufacturing method thereof, and a display device are disclosed. The display panel includes an array substrate and a counter substrate. The array substrate includes a main region and a peripheral region, the main region coincides with an orthographical projection of the counter substrate on the array substrate, and at least one glue dispensing zone is arranged in the peripheral region or the main region. Conductive adhesive is provided in the glue dispensing zone, and is electrically connected to a grounded unit; an electrostatic conducting structure is provided on the counter substrate, and the conductive adhesive is electrically connected to the electrostatic conducting structure.
    Type: Application
    Filed: June 15, 2015
    Publication date: November 10, 2016
    Inventors: Weihua JIA, Peng JIANG, Haipeng YANG, Jaikwang KIM, Yong Jun YOON
  • Publication number: 20160013209
    Abstract: The present invention provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a gate electrode, an active layer, an etch stop layer, a source electrode and a drain electrode, the etch stop layer is provided between the active layer and the source and drain electrodes, a first via hole and a second via hole are formed in the etch stop layer, the source electrode is connected with the active layer through the first via hole, the drain electrode is connected with the active layer through the second via hole, and the gate electrode is overlapped with a part of the first via hole and a part of the second via hole respectively and is overlapped with a portion between the first via hole and the second via hole.
    Type: Application
    Filed: June 30, 2014
    Publication date: January 14, 2016
    Inventors: Haipeng YANG, Yongjun YOON, Zhizhong TU, Jaikwang KIM
  • Patent number: 9196735
    Abstract: The present invention discloses a thin film transistor and a method for manufacturing the same, an array substrate and a display device. The performance of the thin film transistor can be improved and thereby the image quality can be improved by an increase in the width of the conducting area of a thin film transistor without change of the capacitance of the source electrode. The thin film transistor comprises a substrate, a gate electrode, a source electrode, at least two drain electrodes, a semiconductor layer, a gate electrode protection layer located between the gate electrode and the semiconductor layer and an etch stopping layer located between the semiconductor layer and the source electrode with the drain electrode, wherein the source electrode and the drain electrodes are respectively connected with the semiconductor layer by a via hole.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: November 24, 2015
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Haipeng Yang, Yong Jun Yoon, Zhizhong Tu, Jai Kwang Kim
  • Publication number: 20140103345
    Abstract: The present invention discloses a thin film transistor and a method for manufacturing the same, an array substrate and a display device. The performance of the thin film transistor can be improved and thereby the image quality can be improved by an increase in the width of the conducting area of a thin film transistor without change of the capacitance of the source electrode. The thin film transistor comprises a substrate, a gate electrode, a source electrode, at least two drain electrodes, a semiconductor layer, a gate electrode protection layer located between the gate electrode and the semiconductor layer and an etch stopping layer located between the semiconductor layer and the source electrode with the drain electrode, wherein the source electrode and the drain electrodes are respectively connected with the semiconductor layer by a via hole.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 17, 2014
    Applicants: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haipeng Yang, Yong Jun Yoon, Zhizhong Tu, Jai Kwang Kim