Patents by Inventor Hajime Akiyama
Hajime Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240304439Abstract: A substrate processing method includes: forming a metal film, which changes in volume when the metal film is oxidized, on a rear surface of a substrate; forming an oxide film, through which oxygen permeates, on a front surface of the metal film; and applying stress to the substrate by oxidizing the metal film.Type: ApplicationFiled: January 13, 2022Publication date: September 12, 2024Inventors: Koji AKIYAMA, Philippe GAUBERT, Hajime NAKABAYASHI, Chihiro TAMURA, Hisashi WARASHINA
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Patent number: 10868123Abstract: The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n? type drift region and not penetrating a SiC substrate; an n+ type side surface diffusion region formed on each side surface of the first trench; an n+ type bottom diffusion region formed under the n? type drift region and in contact with the n+ type side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the n? type drift region at regular spacings of 0.4 ?m or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.Type: GrantFiled: June 14, 2019Date of Patent: December 15, 2020Assignee: Mitsubishi Electric CorporationInventors: Hajime Akiyama, Manabu Yoshino
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Publication number: 20200027954Abstract: The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n? type drift region and not penetrating a SiC substrate; an n+ type side surface diffusion region formed on each side surface of the first trench; an n+ type bottom diffusion region formed under the n? type drift region and in contact with the n+ type side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the n? type drift region at regular spacings of 0.4 ?m or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.Type: ApplicationFiled: June 14, 2019Publication date: January 23, 2020Applicant: Mitsubishi Electric CorporationInventors: Hajime AKIYAMA, Manabu YOSHINO
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Patent number: 10228129Abstract: Problem to be Solved To provide a waste gasification melting apparatus which, even if a fuel gas is used as an alternative to a part of the coke, the temperature of the coke bed can be sufficiently raised, and a method using the same. Solution A waste gasification melting apparatus including an oxygen rich air supply apparatus 14 for blowing oxygen rich air into a tuyere 5, and a fuel gas supply apparatus 15 for supplying a fuel gas to the tuyere 5, and a controller 16 for controlling the oxygen rich air supply apparatus 14; the oxygen rich air supply apparatus 14 mixing air and oxygen to prepare oxygen rich air and supply the oxygen rich air to the tuyere 5; and the controller 16 controlling the amount of air to be mixed and the amount of oxygen to be mixed in the oxygen rich air supply apparatus 14 so as to give an oxygen concentration of the oxygen rich air in accordance with the amount of fuel gas supplied to the tuyere 5 from the fuel gas supply apparatus 15.Type: GrantFiled: March 27, 2014Date of Patent: March 12, 2019Assignee: JFE Engineering CorporationInventors: Satoshi Horiuchi, Keiichi Okuyama, Takeshi Uchiyama, Hajime Akiyama, Junya Watanabe, Takashi Nakayama, Kazumasa Wakimoto, Akio Shimomura
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Patent number: 10228412Abstract: A purpose of the present invention is to provide a technique capable of suppressing an electric discharge during evaluation. A semiconductor device includes: a semiconductor base body having an element region and a terminal region; a plurality of electrode pads disposed in an area that is in the element region of the semiconductor base body and is separated from the terminal region, an insulating protection film having an opening provided above each of the electrode pads; and a plurality of conductive layers disposed on the protection film and electrically connected to the plurality of electrode pads, respectively, through the opening. In a planar view, each of the conductive layers is extended to the terminal region or the vicinity of the terminal region.Type: GrantFiled: March 6, 2014Date of Patent: March 12, 2019Assignee: Mitsubishi Electric CorporationInventors: Hajime Akiyama, Akira Okada, Kinya Yamashita
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Patent number: 10192797Abstract: A purpose of the present invention is to provide a semiconductor device that can restrain occurrence of partial discharge in evaluation of electric characteristics and can carry out failure analysis from the upper side of a measurement object. A semiconductor device according to the present invention includes: at least one electrode; a protective layer having at least one opening part provided such that a portion of the electrode is exposed at the opening part, and being formed to cover the other portion of the electrode excluding the portion of the electrode exposed at the opening part, the protective layer being insulative; and a conductive layer formed so as to cover the protective layer and the opening part and be directly connected to the electrode at the opening part.Type: GrantFiled: March 6, 2014Date of Patent: January 29, 2019Assignee: Mitsubishi Electric CorporationInventors: Hajime Akiyama, Akira Okada, Kinya Yamashita
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Patent number: 10068814Abstract: An apparatus for evaluating a semiconductor device includes: a chuck stage for fixing a semiconductor device; an insulating substrate; a plurality of probes fixed to the insulating substrate; a temperature adjustment unit adjusting temperatures of the plurality of probes; an evaluation/control unit causing a current to flow into the semiconductor device through the plurality of probes to evaluate an electric characteristic of the semiconductor device; an inspection plate having a front surface and a rear surface opposite to each other; a thermal image measurement unit acquiring a thermal image of the inspection plate when distal end portions of the plurality of probes are pressed against the front surface; and a thermal image processing unit performing image processing to the thermal image to obtain in-plane positions and temperatures of the distal end portions of the plurality of probes.Type: GrantFiled: April 22, 2016Date of Patent: September 4, 2018Assignee: Mitsubishi Electric CorporationInventors: Akira Okada, Norihiro Takesako, Hajime Akiyama
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Patent number: 9995786Abstract: An apparatus for evaluating a semiconductor device includes: a chuck stage; an insulating substrate; a plurality of probes; a temperature adjustment unit; an evaluation/control unit; and a probe position/temperature inspection device including an inspection plate, a thermo-chromic material, a photographing unit, and an image processing unit. The photographing unit photographs a color-change image of the thermo-chromic material in a state in which distal end portions of the plurality of probes are pressed against the upper surface of the inspection plate. The image processing unit performs image processing to the color-change image to calculate in-plane positions and temperatures of the distal end portions of the plurality of probes.Type: GrantFiled: July 7, 2016Date of Patent: June 12, 2018Assignee: Mitsubishi Electric CorporationInventors: Akira Okada, Norihiro Takesako, Hajime Akiyama
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Patent number: 9880196Abstract: A semiconductor device inspection apparatus includes probe sockets and an insulating plate that holds probes via the probe sockets. The probe sockets each include an opposing part that opposes the insulating plate in the direction in which the probe is pressed and has a pressure passive member disposed in the opposing part. The insulating plate is transparent. When pressing force is applied to the tips of the probes, the pressure passive members are pressed between the opposing parts of the probe sockets and the insulating plate. The semiconductor device inspection apparatus further includes a camera to capture an image of the pressure passive members from the opposite side of the insulating plate to the side on which the pressure passive members are disposed, and an image processor to process the image captured by the camera to detect the presence or absence of pressure received by the pressure passive members.Type: GrantFiled: September 19, 2016Date of Patent: January 30, 2018Assignee: Mitsubishi Electric CorporationInventors: Hajime Akiyama, Akira Okada
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Publication number: 20170205442Abstract: A semiconductor device inspection apparatus includes probe sockets and an insulating plate that holds probes via the probe sockets. The probe sockets each include an opposing part that opposes the insulating plate in the direction in which the probe is pressed and has a pressure passive member disposed in the opposing part. The insulating plate is transparent. When pressing force is applied to the tips of the probes, the pressure passive members are pressed between the opposing parts of the probe sockets and the insulating plate. The semiconductor device inspection apparatus further includes a camera to capture an image of the pressure passive members from the opposite side of the insulating plate to the side on which the pressure passive members are disposed, and an image processor to process the image captured by the camera to detect the presence or absence of pressure received by the pressure passive members.Type: ApplicationFiled: September 19, 2016Publication date: July 20, 2017Applicant: Mitsubishi Electric CorporationInventors: Hajime AKIYAMA, Akira OKADA
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Patent number: 9678143Abstract: A semiconductor evaluation apparatus includes a jig for evaluation and a probe substrate. The jig for evaluation is provided such that a plurality of semiconductor devices can be placed thereon. The probe substrate is provided so as to face the jig for evaluation, and includes a contact probe. The jig for evaluation includes a plurality of housing portions divided by a frame portion such that the plurality of semiconductor devices can be separately placed on the plurality of housing portions, respectively. The semiconductor evaluation apparatus is configured such that the contact probe can be brought into contact with a plurality of elements in the state where a space is provided by bringing the frame portion and the probe substrate in proximity to each other. In this space, each of the plurality of semiconductor devices is placed between a corresponding one of the plurality of housing portions and the probe substrate.Type: GrantFiled: June 17, 2014Date of Patent: June 13, 2017Assignee: Mitsubishi Electric CorporationInventors: Akira Okada, Takaya Noguchi, Norihiro Takesako, Kinya Yamashita, Hajime Akiyama
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Patent number: 9659795Abstract: A device includes a jig having a plate with through-holes formed therein and also having a frame formed on the plate so as to be able to accommodate a plurality of semiconductor chips in spaced relationship, a foreign matter capture member having a first charge section with a first flat surface and a second charge section with a second flat surface, the second charge section being insulated from the first charge section, charging means for positively charging the first flat surface and negatively charging the second flat surface, and sliding means for causing either the jig or the foreign matter capture member to slide relative to the other in such a manner that the through-holes of the jig are spaced a predetermined distance from the first and second flat surfaces. The through-holes are formed in different regions defined and surrounded by the frame.Type: GrantFiled: September 14, 2012Date of Patent: May 23, 2017Assignee: Mitsubishi Electric CorporationInventors: Akira Okada, Takaya Noguchi, Hajime Akiyama
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Publication number: 20170139002Abstract: An apparatus for evaluating a semiconductor device includes: a chuck stage; an insulating substrate; a plurality of probes; a temperature adjustment unit; an evaluation/control unit; and a probe position/temperature inspection device including an inspection plate, a thermo-chromic material, a photographing unit, and an image processing unit. The photographing unit photographs a color-change image of the thermo-chromic material in a state in which distal end portions of the plurality of probes are pressed against the upper surface of the inspection plate. The image processing unit performs image processing to the color-change image to calculate in-plane positions and temperatures of the distal end portions of the plurality of probes.Type: ApplicationFiled: July 7, 2016Publication date: May 18, 2017Applicant: Mitsubishi Electric CorporationInventors: Akira OKADA, Norihiro TAKESAKO, Hajime AKIYAMA
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Publication number: 20170092553Abstract: An apparatus for evaluating a semiconductor device includes: a chuck stage for fixing a semiconductor device; an insulating substrate; a plurality of probes fixed to the insulating substrate; a temperature adjustment unit adjusting temperatures of the plurality of probes; an evaluation/control unit causing a current to flow into the semiconductor device through the plurality of probes to evaluate an electric characteristic of the semiconductor device; an inspection plate having a front surface and a rear surface opposite to each other; a thermal image measurement unit acquiring a thermal image of the inspection plate when distal end portions of the plurality of probes are pressed against the front surface; and a thermal image processing unit performing image processing to the thermal image to obtain in-plane positions and temperatures of the distal end portions of the plurality of probes.Type: ApplicationFiled: April 22, 2016Publication date: March 30, 2017Applicant: Mitsubishi Electric CorporationInventors: Akira OKADA, Norihiro TAKESAKO, Hajime AKIYAMA
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Patent number: 9551745Abstract: A semiconductor device assessment apparatus that electrically assesses a semiconductor device formed on a semiconductor substrate includes a holding unit having a surface to hold the semiconductor substrate thereon, and a detection unit to detect irregularity on the surface of the holding unit. The holding unit on the surface includes a plurality of grooves formed such that when the semiconductor substrate is held on the surface, the grooves overlap a periphery of the semiconductor substrate and also have a portion located outer than the periphery of the semiconductor substrate.Type: GrantFiled: February 24, 2014Date of Patent: January 24, 2017Assignee: Mitsubishi Electric CorporationInventors: Hajime Akiyama, Akira Okada, Kinya Yamashita
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Publication number: 20160377486Abstract: A temperature detecting probe as a contact-probe type temperature detector includes a plunger portion contactable with a semiconductor device as an object to be measured, a spring member placed on a base end portion of the plunger portion, a barrel portion pressing the plunger portion the semiconductor device side with the spring member interposed therebetween, and a thermocouple as a temperature measuring portion detecting a temperature of the semiconductor device.Type: ApplicationFiled: March 8, 2016Publication date: December 29, 2016Applicant: Mitsubishi Electric CorporationInventors: Kinya YAMASHITA, Takaya NOGUCHI, Akira OKADA, Hajime AKIYAMA, Masaki UENO
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Publication number: 20160343627Abstract: A purpose of the present invention is to provide a semiconductor device that can restrain occurrence of partial discharge in evaluation of electric characteristics and can carry out failure analysis from the upper side of a measurement object. A semiconductor device according to the present invention includes: at least one electrode; a protective layer having at least one opening part provided such that a portion of the electrode is exposed at the opening part, and being formed to cover the other portion of the electrode excluding the portion of the electrode exposed at the opening part, the protective layer being insulative; and a conductive layer formed so as to cover the protective layer and the opening part and be directly connected to the electrode at the opening part.Type: ApplicationFiled: March 6, 2014Publication date: November 24, 2016Applicant: Mitsubishi Electric CorporationInventors: Hajime AKIYAMA, Akira OKADA, Kinya YAMASHITA
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Publication number: 20160334458Abstract: A purpose of the present invention is to provide a technique capable of suppressing an electric discharge during evaluation. A semiconductor device includes: a semiconductor base body having an element region and a terminal region; a plurality of electrode pads disposed in an area that is in the element region of the semiconductor base body and is separated from the terminal region, an insulating protection film having an opening provided above each of the electrode pads; and a plurality of conductive layers disposed on the protection film and electrically connected to the plurality of electrode pads, respectively, through the opening. In a planar view, each of the conductive layers is extended to the terminal region or the vicinity of the terminal region.Type: ApplicationFiled: March 6, 2014Publication date: November 17, 2016Applicant: Mitsubishi Electric CorporationInventors: Hajime AKIYAMA, Akira OKADA, Kinya YAMASHITA
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Patent number: 9347988Abstract: A semiconductor testing jig fixes a measurement target while it is held between a chuck stage and the measurement target. The semiconductor testing jig includes a base on which the measurement target is to be installed and which can be attached to the chuck stage. The base includes: a first main surface to become an installation surface for the measurement target; a second main surface opposite the first main surface and which is to contact the chuck stage; and a porous region containing a porous member. The porous region is provided selectively as seen in plan view, and penetrates through the base from the first main surface toward the second main surface.Type: GrantFiled: March 14, 2013Date of Patent: May 24, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Hajime Akiyama, Akira Okada, Kinya Yamashita
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Patent number: 9335371Abstract: A semiconductor evaluating device includes a chuck stage for holding a semiconductor device serving as a measuring object, a contact probe for evaluating an electrical characteristic of the semiconductor device by getting contact with the semiconductor device held on the chuck stage, and a fluid spraying portion for spraying a fluid onto the semiconductor device.Type: GrantFiled: October 28, 2013Date of Patent: May 10, 2016Assignee: Mitsubishi Electric CorporationInventors: Hajime Akiyama, Akira Okada, Kinya Yamashita