Patents by Inventor Hajime Akiyama
Hajime Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110053348Abstract: The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved.Type: ApplicationFiled: November 8, 2010Publication date: March 3, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Hajime Akiyama
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Patent number: 7851873Abstract: The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved.Type: GrantFiled: May 20, 2008Date of Patent: December 14, 2010Assignee: Mitsubishi Electric CorporationInventor: Hajime Akiyama
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Patent number: 7777279Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).Type: GrantFiled: June 30, 2008Date of Patent: August 17, 2010Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazunari Hatade, Hajime Akiyama, Kazuhiro Shimizu
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Patent number: 7545005Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).Type: GrantFiled: June 30, 2008Date of Patent: June 9, 2009Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazunari Hatade, Hajime Akiyama, Kazuhiro Shimizu
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Publication number: 20090140377Abstract: A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive type having a high impurity concentration, a second semiconductor region of a second conductive type having a high impurity concentration arranged so as to surround the first semiconductor region, a first main electrode joined to a surface of the first semiconductor region, and a second main electrode joined to a surface of the second semiconductor region. A first dielectric portion is arranged adjacent the embedded dielectric layer so as to surround a region of the support substrate superposed on the first semiconductor region in a direction of lamination thereof, and a wire connected with the first main electrode.Type: ApplicationFiled: December 29, 2008Publication date: June 4, 2009Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Hajime Akiyama
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Publication number: 20090127637Abstract: The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved.Type: ApplicationFiled: May 20, 2008Publication date: May 21, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Hajime AKIYAMA
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Publication number: 20090096091Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.Type: ApplicationFiled: December 11, 2008Publication date: April 16, 2009Inventors: Kazuhiro Shimizu, Hajime Akiyama, Naoki Yasuda
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Patent number: 7485943Abstract: A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive type having a high impurity concentration, a second semiconductor region of a second conductive type having a high impurity concentration arranged so as to surround the first semiconductor region, a first main electrode joined to a surface of the first semiconductor region, and a second main electrode joined to a surface of the second semiconductor region. A first dielectric portion is arranged adjacent the embedded dielectric layer so as to surround a region of the support substrate superposed on the first semiconductor region in a direction of lamination thereof, and a wire connected with the first main electrode.Type: GrantFiled: April 21, 2006Date of Patent: February 3, 2009Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hajime Akiyama
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Patent number: 7481885Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which ejects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.Type: GrantFiled: April 28, 2006Date of Patent: January 27, 2009Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuhiro Shimizu, Hajime Akiyama, Naoki Yasuda
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Publication number: 20080272440Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).Type: ApplicationFiled: June 30, 2008Publication date: November 6, 2008Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kazunari HATADE, Hajime AKIYAMA, Kazuhiro SHIMIZU
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Publication number: 20080265334Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).Type: ApplicationFiled: June 30, 2008Publication date: October 30, 2008Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kazunari HATADE, Hajime AKIYAMA, Kazuhiro SHIMIZU
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Patent number: 7417296Abstract: A dielectric isolation type semiconductor device can achieve high dielectric resistance while preventing the dielectric strength thereof from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A drift N? region is bonded to a semiconductor substrate through a buried oxide film to from a high withstand-voltage device in the drift N? region. A first field plate is formed on the drift N? region in the vicinity of a drain electrode. A first high silicon concentration region composed of a buried N+ region is formed in a porous oxide film region forming a part of the buried oxide film at a location right under the drain electrode. The drain electrode and the first field plate are electrically connected to the first high silicon concentration region through a drain N? well region.Type: GrantFiled: April 13, 2005Date of Patent: August 26, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hajime Akiyama
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Patent number: 7408228Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).Type: GrantFiled: January 17, 2007Date of Patent: August 5, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazunari Hatade, Hajime Akiyama, Kazuhiro Shimizu
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Publication number: 20070114614Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).Type: ApplicationFiled: January 17, 2007Publication date: May 24, 2007Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kazunari Hatade, Hajime Akiyama, Kazuhiro Shimizu
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Publication number: 20070072394Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.Type: ApplicationFiled: April 28, 2006Publication date: March 29, 2007Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kazuhiro Shimizu, Hajime Akiyama, Naoki Yasuda
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Patent number: 7190034Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).Type: GrantFiled: September 20, 2005Date of Patent: March 13, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazunari Hatade, Hajime Akiyama, Kazuhiro Shimizu
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Patent number: 7135752Abstract: A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A semiconductor substrate (1) and an n? type semiconductor layer (2) are bonded to each other through a buried oxide film layer (3). A first porous oxide film area (10) is formed in the semiconductor substrate in a state contacting with the buried oxide film layer. A power device is formed on the n? type semiconductor layer. The first porous oxide film area is formed in an area including a location right under a first main electrode (6) and extending from the first main electrode side up to a range of more than 40% of a distance (L) between the first and second main electrodes (6, 7).Type: GrantFiled: November 8, 2004Date of Patent: November 14, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hajime Akiyama, Shinichi Izuo
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Publication number: 20060249807Abstract: A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive type having a high impurity concentration, a second semiconductor region of a second conductive type having a high impurity concentration arranged so as to surround the first semiconductor region, a first main electrode joined to a surface of the first semiconductor region, and a second main electrode joined to a surface of the second semiconductor region. A first dielectric portion is arranged adjacent the embedded dielectric layer so as to surround a region of the support substrate superposed on the first semiconductor region in a direction of lamination thereof, and a wire connected with the first main electrode.Type: ApplicationFiled: April 21, 2006Publication date: November 9, 2006Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Hajime Akiyama
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Patent number: 7125780Abstract: A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A semiconductor substrate (1) and an n? type semiconductor layer (2) are bonded to each other through a buried oxide film layer (3). A first porous oxide film area (10) is formed in the semiconductor substrate in a state contacting with the buried oxide film layer. A power device is formed on the n? type semiconductor layer. The first porous oxide film area is formed in an area including a location right under a first main electrode (6) and extending from the first main electrode side up to a range of more than 40% of a distance (L) between the first and second main electrodes (6, 7).Type: GrantFiled: February 16, 2006Date of Patent: October 24, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hajime Akiyama, Shinichi Izuo
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Publication number: 20060138586Abstract: A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A semiconductor substrate (1) and an n? type semiconductor layer (2) are bonded to each other through a buried oxide film layer (3). A first porous oxide film area (10) is formed in the semiconductor substrate in a state contacting with the buried oxide film layer. A power device is formed on the n? type semiconductor layer. The first porous oxide film area is formed in an area including a location right under a first main electrode (6) and extending from the first main electrode side up to a range of more than 40% of a distance (L) between the first and second main electrodes (6, 7).Type: ApplicationFiled: February 16, 2006Publication date: June 29, 2006Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hajime Akiyama, Shinichi Izuo