Abstract: A tag data processing apparatus is described for use in a data flow computer utilizing a tagged token scheme. A tag adding process and tag restoring process are executed by using pipeline registers, a queue memory and simple control circuit, thereby obtaining high speed operation and superior throughput without the need for a tag memory table, complicated operation-test circuitry or a sequence control circuit.

Abstract: In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module. The daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Abstract: A coincidence element responsive to a plurality of input signals for outputting the level of the input signals when said plurality of input signals coincide with each other includes, a serial connection of a first electrically conductive type and a second electrically conductive type MOS transistors of the same number, the number being equal to the number of the input signals, responsive to said plurality of inputs connected between a first power supply and a second power supply; and a CMOS inverter responsive to an intermediate output at the connection of the most lower stage first conductivity type MOS transistor and the most upper stage second conductivity type MOS transistor for outputting a coincidence signal.

Abstract: A simulation method and a computer therefor, i.e., a simulator, for simulating operation of a circuit employing logic gates. The simulation method is to be called the event drive method, in which the output processing is executed only when an input to cause output changes and the output level and the start and finish time for the level are sent out. Hence the number of packets of data flowing for simulation can be minimized and also the number of times of data processing is reduced. This system is applied to each component in a logic circuit, whereby the parallel execution of processing as to the parallel components is possible so as to devise the simulation at a higher speed.