Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer i

Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer i

Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer.

Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

Abstract: A display panel includes a common electrode formed in an upper layer above a data line, a first insulating layer covering the common electrode, a touch sensor line formed in an upper layer of the first insulating layer and in a first opening provided in the first insulating layer, and connected to the common electrode via the first opening, a second insulating layer covering the touch sensor line, and a pixel electrode formed in an upper layer of the second insulating layer. The first insulating layer is formed with a second opening between the common electrode and the pixel electrode. The second insulating layer is disposed in an interior of the second opening and formed with a recessed portion recessed downward into a portion above the second opening. At least a portion of the pixel electrode is disposed in the recessed portion of the second insulating layer.

Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

Abstract: A display device includes a switching element having a pixel connection portion, a first insulating film having a first pixel contact hole formed therein so as to be in a place overlapping at least a part of the pixel connection portion, a common line, an intermediate electrode composed of the same conducting film as the common line, disposed to overlap the first pixel contact hole, and connected to the pixel connection portion, a common electrode not connected to the intermediate electrode but connected to the common line, a second insulating film having a second pixel contact hole formed therein so as to be in a place overlapping at least a part of the intermediate electrode, and a pixel electrode disposed so that at least a part of the pixel electrode overlaps the second pixel contact hole.

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.

Abstract: An active matrix substrate includes a first TFT and a second TFT, in which the first TFT includes a first oxide semiconductor layer and a first gate electrode arranged on a part of the first oxide semiconductor layer with a first gate insulating layer interposed therebetween, the first gate insulating layer has a layered structure including a first insulating film and a second insulating film arranged on the first insulating film, the second TFT includes a second oxide semiconductor layer having a higher mobility than the first oxide semiconductor layer and a second gate electrode arranged on a part of the second oxide semiconductor layer with a second gate insulating layer interposed therebetween, and the second gate insulating layer includes the second insulating film and does not include the first insulating film, and the second TFT further includes a lower insulating layer including the first insulating film arranged between the second oxide semiconductor layer and a substrate.

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer i

Abstract: An active matrix substrate includes gate bus lines; source bus lines; a lower insulating layer; an oxide semiconductor TFT; and a pixel electrode, in which the oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode, a source electrode, and a first ohmic conductive portion that is coupled to the oxide semiconductor layer and the source electrode, the lower insulating layer includes a source opening portion exposing at least a portion of the source electrode, the first ohmic conductive portion is disposed on the lower insulating layer and in the source opening portion and is in direct contact with at least the portion of the source electrode in the source opening portion, and the first region of the oxide semiconductor layer is in direct contact with an upper surface of the first ohmic conductive portion.

Abstract: An in-cell touch panel includes a plurality of source lines, a source redundant line, a touch sensor line formed in the same layer as the plurality of source lines or the source redundant line, an organic insulating layer formed in a layer above the touch sensor line, and a common electrode formed in a layer above the organic insulating layer. A contact hole in which part of the common electrode is arranged is formed in the organic insulating layer above the touch sensor line, and the common electrode is connected to the touch sensor line via the contact hole.

Abstract: An active matrix substrate includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate, in which each of oxide semiconductor TFT includes an oxide semiconductor layer including a first region and a second region having a specific resistance lower than a specific resistance of the first region, and a gate electrode disposed on at least a part of the first region with a gate insulating layer interposed therebetween, the gate insulating layer includes a first insulating layer and a second insulating layer disposed on the first insulating layer, and, when viewed from a normal direction of the substrate, the first insulating layer overlaps with the first region and does not overlap with the second region and the second insulating layer overlaps with the first region and at least a part of the second region.

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

Abstract: A display panel includes a common electrode formed in an upper layer above a data line, a first insulating layer covering the common electrode, a touch sensor line formed in an upper layer of the first insulating layer and in a first opening provided in the first insulating layer, and connected to the common electrode via the first opening, a second insulating layer covering the touch sensor line, and a pixel electrode formed in an upper layer of the second insulating layer. The first insulating layer is formed with a second opening between the common electrode and the pixel electrode. The second insulating layer is disposed in an interior of the second opening and formed with a recessed portion recessed downward into a portion above the second opening. At least a portion of the pixel electrode is disposed in the recessed portion of the second insulating layer.