Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.

Abstract: The present invention provides a thin-film transistor array substrate that prevents semiconductor layers of thin-film transistor elements from having step disconnection even when the frame width is reduced. The thin-film transistor array substrate of the present invention includes a thin-film transistor element in a pixel region and a terminal in a terminal region. The thin-film transistor array substrate sequentially includes a support, an insulating layer, a gate electrode, a gate insulating layer, and a semiconductor layer in a cross-sectional view of the pixel region. A region with the insulating layer encompasses a region with the semiconductor layer in a plan view of the pixel region. The thin-film transistor array substrate sequentially includes the support, a lead line extending from the terminal, and the insulating layer in a cross-sectional view of the terminal region.

Abstract: The present invention provides a thin-film transistor array substrate that prevents semiconductor layers of thin-film transistor elements from having step disconnection even when the frame width is reduced. The thin-film transistor array substrate of the present invention includes a thin-film transistor element in a pixel region and a terminal in a terminal region. The thin-film transistor array substrate sequentially includes a support, an insulating layer, a gate electrode, a gate insulating layer, and a semiconductor layer in a cross-sectional view of the pixel region. A region with the insulating layer encompasses a region with the semiconductor layer in a plan view of the pixel region. The thin-film transistor array substrate sequentially includes the support, a lead line extending from the terminal, and the insulating layer in a cross-sectional view of the terminal region.

Abstract: An active matrix substrate includes TFTs, an interlayer insulating layer, a common electrode, a first dielectric layer, pixel electrodes, a second dielectric layer, and touch wirings, in which each of the pixel electrodes at least partially overlaps the common electrode via the first dielectric layer, so that an auxiliary capacitance including each of the pixel electrodes, the common electrode, and the first dielectric layer is formed, the touch sensor electrodes include a first electrode, the touch wirings include a first wiring and a second wiring in the touch sensor electrodes, the second wiring extends to the other electrode across the first electrode when viewed from a normal direction, and a portion of the second wiring overlaps the first electrode via the first and the second dielectric layers, so that a touch wiring capacitance including the second wiring, the first electrode, the first and the second dielectric layers is formed.

Abstract: An active-matrix substrate according to an embodiment of the present invention includes a plurality of first TFTs that are arranged within a display area, an inorganic insulating layer that covers the plurality of first TFTs, an organic insulating layer that is provided on the inorganic insulating layer, a plurality of second TFTs that are arranged within a non-display area, and a source and gate metal connection portion that is positioned within the non-display area, a first conductive layer that is formed from an identical conductive film with a gate wiring line and a second conductive layer that is formed from an identical conductive film with a source wiring line being connected to each other at the source and gate metal connection portion. Each of the plurality of first TFTs is an oxide semiconductor TFT. At least one second TFT among the plurality of second TFTs is covered with the organic insulating layer. The source and gate metal connection portion is not covered with the organic insulating layer.

Abstract: An active matrix substrate 10 includes: switching elements 120 that are connected with gate lines and data lines provided on a substrate; pixel electrodes 130 that are connected with the switching elements 120; counter electrodes 140 that overlap with the pixel electrodes 130 when viewed in a plan view; a flattening film 154; and lines 142. The flattening film 154 covers the switching elements 120, and first contact holes CH1 that pass through the flattening film 154 are formed at positions that overlap with the lines 142 when viewed in a plan view. The pixel electrodes 130 and the counter electrodes 140 are arranged so that each of the same partially covers the flattening film 154. The line 142 and the counter electrode 140 are connected with each other in the first contact hole CH1.

Abstract: An active matrix substrate includes gate bus lines; source bus lines; a lower insulating layer; an oxide semiconductor TFT; and a pixel electrode, in which the oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode, a source electrode, and a first ohmic conductive portion that is coupled to the oxide semiconductor layer and the source electrode, the lower insulating layer includes a source opening portion exposing at least a portion of the source electrode, the first ohmic conductive portion is disposed on the lower insulating layer and in the source opening portion and is in direct contact with at least the portion of the source electrode in the source opening portion, and the first region of the oxide semiconductor layer is in direct contact with an upper surface of the first ohmic conductive portion.

Abstract: A semiconductor device (100) includes a TFT (10) supported on a substrate (11), wherein the TFT (10) includes a gate electrode (12g), a gate insulating layer (14) that covers the gate electrode (12g), and an oxide semiconductor layer (16) that is formed on the gate insulating layer (14). The oxide semiconductor layer 16 has a layered structure including a first oxide semiconductor layer (16a) in contact with the gate insulating layer (14) and a second oxide semiconductor layer (16b) layered on the first oxide semiconductor layer (16a). The first oxide semiconductor layer (16a) and the second oxide semiconductor layer (16b) both include In, Ga and Zn; an In atomic ratio of the first oxide semiconductor layer (16a) is greater than a Zn atomic ratio thereof, and an In atomic ratio of the second oxide semi-conductor layer (16b) is smaller than a Zn atomic ratio thereof; and the oxide semiconductor layer (16) has a side surface of a forward tapered shape.

Abstract: An active matrix substrate includes a substrate; a plurality of gate bus lines and a plurality of source bus lines; an oxide semiconductor TFT that includes an oxide semiconductor layer, a gate insulating layer, and a gate electrode; a pixel electrode; and an upper insulating layer. The oxide semiconductor layer includes a high resistance region, and a first region and a second region. The high resistance region includes a channel region, a first channel offset region, and a second channel offset region. The upper insulating layer is disposed so as to overlap the channel region, the first channel offset region, and the second channel offset region, and so as not to overlap any of the first region and the second region, when viewed from the normal direction of the main surface of the substrate.

Abstract: An active matrix substrate includes: a source metal layer including a plurality of source bus lines; a lower insulating layer covering the source metal layer; a oxide semiconductor TFT including an oxide semiconductor layer provided on the lower insulating layer; an inter-layer insulating layer covering the oxide semiconductor TFT; a pixel electrode provided on the inter-layer insulating layer; a common electrode including a plurality of sub common electrodes each of which is capable of functioning as a touch sensor electrode; a gate metal layer including a plurality of gate bus lines and a gate electrode; a drain metal layer including the drain electrode; and a plurality of touch sensor lines included in the drain metal layer and each electrically connected to any one of the sub common electrodes.

Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs, a plurality of gate bus lines, a plurality of source bus lines, and at least one trunk wiring provided in a non-display region and transmitting a signal, and a plurality of other wirings, each of which is disposed so as to at least partially overlap the trunk wirings. The active matrix substrate includes a first metal layer, a second metal layer disposed above the first metal layer, and a third metal layer disposed above the second metal layer on the substrate. One of the first, second, and third metal layers includes a source bus line, and other layer includes a gate bus line. The trunk wiring is formed in two metal layer of the first, second and third metal layers.

Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.

Abstract: An active matrix substrate includes: a substrate; lower bus lines and upper bus lines; a lower insulating layer positioned between the lower bus lines and the upper bus lines; an oxide semiconductor TFT that are disposed in each pixel region and have an oxide semiconductor layer disposed on the lower insulating layer; pixel electrodes disposed in each pixel region; and wiring connection units arranged in a non-display region. Each wiring connection unit includes: a lower conductive layer formed using the same conductive film as the lower bus lines; an insulating layer that extends on the lower conductive layer and includes the lower insulating layer. The lower bus lines and the lower conductive layer have a first laminated structure including a metal layer and a transparent conductive layer that covers an upper surface and a side surface of the metal layer.

Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode.

Abstract: A semiconductor device includes a first TFT, a first source-side connection section that is formed from a part of a second metal film and connected to a first source region, a first drain-side connection section that is formed from a part of the second metal film and connected to a first drain region, a second TFT that is driven by the first TFT, a second source-side connection section that is formed from a part of a first metal film and connected to a second source region, and a second drain-side connection section that is formed from a part of the first metal film or a second transparent electrode film and connected to a second drain region.

Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.

Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).

Abstract: A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

Abstract: A method for manufacturing an active matrix board includes (E) a step of forming a source contact hole and a drain contact hole in an interlayer insulating layer such that a portion of a source contact region of an oxide semiconductor layer and a portion of a drain contact region thereof are exposed and forming a connecting portion contact hole in the interlayer insulating layer and a lower insulating layer such that a portion of a lower conductive layer is exposed; and (F) a step of forming a source electrode, a drain electrode, and an upper conductive layer on the interlayer insulating layer; and the step (E) includes (e-1) a step of forming a photoresist film on the interlayer insulating layer and (e-2) a step of forming a photoresist layer in such a manner that the photoresist film is exposed to light using a multi-tone mask and is then developed.