Abstract: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.

Abstract: According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; a gate dielectric film that is formed on the semiconductor substrate; a floating gate electrode film that is formed on the gate dielectric film; an inter-gate dielectric film that includes: a metal oxide film that is formed on the floating gate electrode film; an electron trap film that is formed on the metal oxide film; and a silicon oxide film that is formed on the electron trap film; and a control gate electrode film that is formed on the inter-gate dielectric film.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode film on a semiconductor substrate via a gate insulating film; forming a mask film on the gate electrode film; separating the gate electrode film by using the mask film to form a plurality of gate electrodes; forming a first insulating film between the plurality of gate electrodes so that an upper portion of the first insulating film is lower than an upper surface of the gate electrode; forming a second insulating film on the upper portion of the first insulating film, removing the mask film so as to expose the gate electrode, and cleaning an exposed surface of the gate electrode by wet etching process with selectivity to the second insulating film so as to remove a native oxide film.

Abstract: A semiconductor device manufacturing method includes selectively removing portions of a buried oxide layer and first semiconductor layer in an SOI substrate having the first semiconductor layer formed above a semiconductor substrate with the buried oxide layer disposed therebetween and exposing part of the semiconductor substrate, removing an exposed region of the semiconductor substrate in a depth direction, and burying a second semiconductor region in the region from which part of the semiconductor substrate has been removed in the depth direction.

Abstract: A nonvolatile semiconductor memory including a semiconductor substrate having an upper surface; a plurality of memory cell transistors formed in the semiconductor substrate, each memory cell transistor including a gate electrode having a gate insulating layer on the upper surface of the semiconductor substrate, a floating gate electrode layer on the gate insulating layer, an inter-gate insulating layer on the floating gate electrode layer, and a control gate electrode layer on the inter-gate insulating layer; a first oxide-based insulating film formed above the upper surface of the semiconductor substrate between the gate electrodes, and including an upper surface as high or higher than that of the floating gate electrode layer but lower than that of the control gate electrode layer; a nitride-based insulating film containing boron formed on the first oxide-based insulating film and the control gate layer; and a second oxide-based insulating film formed on the nitride-based insulating film.

Abstract: A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.

Abstract: A wet gas purification method is provided for removing ammonia from a heavy oil gasification gas, such as coal. The method principally involves a washing step during which absorbent is charged into the gas to absorb ammonia and an ammonia treating step wherein absorbent discharged from the washing step is separated into an effluent and an off-gas containing ammonia. The amount of absorbent charged during the washing step is controlled such that the ammonia concentration of gas exiting the washing step is 10 ppm or less.

Abstract: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.

Abstract: A semiconductor device includes a substrate having first and second regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, and a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer, having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and having a tapered surface faced to a side surface of the first epitaxial layer.

Abstract: A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.

Abstract: A semiconductor device including a semiconductor substrate; an element isolation region having a trench filled with an insulating film defined or the semiconductor substrate; a memory cell transistor formed in an element forming region isolated by the element isolating regions of the semiconductor substrate; and the memory cell transistor includes a gate insulating film formed on a surface of the element forming region; a floating gate formed over the gate insulating film; an inter-gate insulating film formed integrally so as to cover the floating gate and the insulating film of the element isolation region and having high dielectric constant in a portion corresponding to the floating gate and low dielectric constant in a portion corresponding to the insulating film of the element isolation region; and a control gate stacked over the floating gate via the inter-gate insulating film.

Abstract: A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.

Abstract: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.

Abstract: There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region and the non-SOI region and having a second insulating film buried therein, the second insulating film being inclined upward from the SOI region side toward the non-SOI region side, the second insulating film having a thickness smaller than the thickness of the first insulating film and being tapered from the SOI region side to the non-SOI region side, a pair of element isolating insulating regions separately formed in the non-SOI region of semiconductor substrate and defining element regions, a pair of impurity diffusion regions formed in the element regions, and a gate electrode formed via a gate insulating film in the element region of the semiconductor substrate.

Abstract: A wireless communication terminal includes a transmission power control unit that changes transmission power; a first storage unit that pre-stores an association of a transmission power value with a difference between a terminal temperature and an ambient temperature; a temperature detection unit that detects a temperature of the terminal to obtain a terminal temperature value; a transmission power detection unit that detects a current transmission power value; a calculation unit that calculates a current ambient temperature value near the terminal; and a temperature estimation unit that estimates a terminal temperature value corresponding to an intended transmission power value based on the current ambient temperature value calculated by the calculation unit, the transmission power value to which the transmission power is changed, and the association of the first storage unit.

Abstract: A wireless communication terminal includes a transmitting unit transmitting data to a wireless base station, a temperature detecting unit detecting a terminal temperature of the inside of the wireless communication terminal, a transmission power detecting unit detecting a transmission power, a memory unit storing plural sets of terminal temperature variation information, and a control unit changing the transmission power based on a state of communication with a wireless base station. The control unit selects and reads one of the plural sets of terminal temperature variation information from a memory unit, based on an ambient temperature, a transmission power, and a changed one of predetermined transmission powers. The control unit controls the transmission state of the data based on the selected one of the plural sets of terminal temperature variation information, so as to prevent the terminal temperature from increasing over an upper limit of a predetermined operation guarantee temperature range.

Abstract: A method of manufacturing a semiconductor device substrate is disclosed, which comprises forming a mask layer patterned on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer deposited thinner on the semiconductor substrate than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.

Abstract: A semiconductor device includes a metal oxide semiconductor (MOS) transistor including two source/drain regions located at a surface layer side of the semiconductor substrate, a stress-inducing film formed so as to cover the source/drain region of the MOS transistor, the stress-inducing film applying stress to a channel region formed between the source/drain regions and having an opening corresponding to an electrical connection region of the source/drain regions, the opening having a first dimension with respect to a propagation direction of a charge carrier moving within the channel region of the MOS transistor and a second dimension with respect to a direction perpendicular to the propagation direction of the MOS transistor, the first dimension being larger than the second dimension.

Abstract: A graded SiGe buffer layer 12 and a SiGe buffer layer 13 are formed on a Si substrate 11. A strained Si layer 14 having a critical film thickness or less is formed to decrease a stress applied to an interface between the strained Si layer 14 and the SiGe buffer layer 13, thereby obtaining a strained Si layer 14, in which a crystal defect density is low. Furthermore, the surface of the strained Si layer 14 is covered by a SiGe cap layer 21, which has a lattice constant greater than Si, thereby preventing the strained Si layer 14 from disappearing due to the sacrifice oxidation performed in the later steps, and enabling a gate oxide layer to be formed thereon. Thus, it is possible to obtain a high-quality strained Si wafer.

Abstract: A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.