Patents by Inventor Hajime Sasaki
Hajime Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11952651Abstract: An Fe-based amorphous alloy ribbon reduced in iron loss, less deformed, and highly productive in a condition of a magnetic flux density of 1.45 T is provided. One aspect of the present disclosure provides an Fe-based amorphous alloy ribbon having first and second surfaces, and is provided with continuous linear laser irradiation marks on at least the first surface. Each linear laser irradiation mark is formed along a direction orthogonal to a casting direction of the Fe-based amorphous alloy ribbon, and has unevenness on its surface. When the unevenness is evaluated in the casting direction, a height difference HL×width WA calculated from the height difference between a highest point and a lowest point in a thickness direction of the Fe-based amorphous alloy ribbon and the width WA which is a length of the linear irradiation mark on the first surface is 6.0 to 180 ?m2.Type: GrantFiled: June 24, 2020Date of Patent: April 9, 2024Assignee: PROTERIAL, LTD.Inventors: Hajime Itagaki, Morifumi Kuroki, Makoto Sasaki, Shin Nakajima
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Publication number: 20240113228Abstract: A semiconductor device according to an embodiment includes: an oxide insulating layer; an oxide semiconductor layer; a gate electrode; a gate insulating layer; and a first insulating layer, wherein the semiconductor device is divided into a first to a third regions, a thickness of the gate insulating layer in the first region is 200 nm or more, the gate electrode contacts the first insulating layer in the first region, the oxide semiconductor layer contacts the first insulating layer in the second region, an amount of impurities contained in the oxide semiconductor layer in the second region is greater than an amount of impurities contained in the oxide semiconductor layer in the first region, and an amount of impurities contained in the oxide insulating layer in the third region is greater than an amount of impurities contained in the oxide insulating layer in the second region.Type: ApplicationFiled: October 3, 2023Publication date: April 4, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Akihiro HANADA, Takaya TAMARU
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Publication number: 20240113227Abstract: A method for manufacturing semiconductor device according to an embodiment includes: forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the metal oxide layer is formed above the gate insulating layer; removing the metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.Type: ApplicationFiled: September 28, 2023Publication date: April 4, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Akihiro HANADA, Takaya TAMARU
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Publication number: 20240105819Abstract: A method for manufacturing a semiconductor device includes depositing a first metal oxide film with aluminum as a major component on a substrate, depositing an amorphous oxide semiconductor film on the first metal oxide film under an oxygen partial pressure of 3% to 5%, processing the oxide semiconductor film into a patterned oxide semiconductor layer, crystallizing the oxide semiconductor layer by performing a first heat treatment on the patterned oxide semiconductor layer, processing the first metal oxide film using the crystallized oxide semiconductor layer as a mask, depositing a gate insulating film on the oxide semiconductor layer, and forming a gate electrode on the gate insulating film, wherein a thickness of the oxide semiconductor film is more than 10 nm and 30 nm or less.Type: ApplicationFiled: September 26, 2023Publication date: March 28, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
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Publication number: 20240097043Abstract: A semiconductor device according to an embodiment of the present invention includes an oxide insulating layer, an oxide semiconductor layer, a gate insulating layer, a gate electrode, and a protective insulating layer. The gate insulating layer includes a first region overlapping the gate electrode and a second region not overlapping the gate electrode. The second region is in contact with the protective insulating layer. The oxide insulating layer includes a third region overlapping the gate electrode and a fourth region not overlapping the gate electrode and the oxide semiconductor layer. The fourth region is in contact with the gate insulating layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. Each of the source region, the drain region, and the second region contains an impurity. A hydrogen concentration of the second region is greater than a hydrogen concentration of the first region.Type: ApplicationFiled: August 28, 2023Publication date: March 21, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takay TAMARU
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Publication number: 20240094481Abstract: An optical apparatus includes a light emitting apparatus and a host apparatus. The light emitting apparatus includes a housing extending in a first direction, a light emitting device mounted in the housing, an optical connector including a first optical connection part provided at one end of the housing, and an electrical connector including a first electrical connection part provided at one end of the housing and receiving a voltage to drive the light emitting device. The host apparatus includes a host optical connector including a second optical connection part which faces the first optical connection part and is optically coupled thereto, a host electrical connector including a second electrical connection part facing the first electrical connection part and being electrically connected to the first electrical connection part, and a host board mounting the host optical connector and the host electrical connector thereon.Type: ApplicationFiled: March 5, 2021Publication date: March 21, 2024Applicants: Sumitomo Electric Industries, Ltd., Sumitomo Electric Device Innovations, Inc.Inventors: Kuniyuki ISHII, Hiromi KURASHIMA, Hideaki KAMISUGI, Tomomi SANO, Tetsuya NAKANISHI, Hong NGUYEN, Hajime ARAO, Dai SASAKI, Takuro WATANABE
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Patent number: 11935729Abstract: The disclosed substrate support includes a first region, a second region, a first electrode, and a second electrode. The first region is configured to hold a substrate placed thereon. The second region is provided to surround the first region and configured to hold an edge ring placed thereon. The first electrode is provided in the first region to receive a first electrical bias. The second electrode is provided in at least the second region to receive a second electrical bias. The second electrode extends below the first electrode to face the first electrode within the first region.Type: GrantFiled: March 2, 2021Date of Patent: March 19, 2024Assignee: Tokyo Electron LimitedInventors: Hajime Tamura, Yasuharu Sasaki, Shin Yamaguchi, Tsuguto Sugawara, Katsuyuki Koizumi
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Patent number: 11935965Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.Type: GrantFiled: April 20, 2023Date of Patent: March 19, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hajime Kimura, Kengo Akimoto, Masashi Tsubuku, Toshinari Sasaki
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Publication number: 20240088302Abstract: A semiconductor device according to an embodiment includes: a substrate; a metal oxide layer arranged above the substrate and having aluminum as the main component of the metal oxide layer; an oxide semiconductor layer arranged above the metal oxide layer; a gate electrode facing the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein a thickness of the metal oxide layer is 1 nm or more and 4 nm or less.Type: ApplicationFiled: September 12, 2023Publication date: March 14, 2024Applicant: Japan Display Inc.Inventors: Takaya TAMARU, Masashi TSUBUKU, Hajime WATAKABE, Toshinari SASAKI
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Publication number: 20240079479Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Inventors: Junichi KOEZUKA, Yukinori SHIMA, Hajime TOKUNAGA, Toshinari SASAKI, Keisuke MURAYAMA, Daisuke MATSUBAYASHI
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Patent number: 11924225Abstract: An information processing apparatus connected to one or more vehicles and a threat information server storing pieces of threat information. The information processing apparatus includes: a processor; and a memory including at least one set of instructions that, when executed by the processor, causes the processor to perform: obtaining a detection result of an attack on one of the vehicles; (a) determining whether the attack is included in any one of the pieces of threat information; (b) when the attack is included therein, determining whether the resolution state to the attack included in the one of the pieces of threat information indicates that the attack has not been resolved or has been resolved; (c) deciding a processing priority level of the attack, based on a determination result in (a) and a determination result in (b); and (d) outputting the processing priority level decided.Type: GrantFiled: November 12, 2020Date of Patent: March 5, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Hajime Tasaki, Takamitsu Sasaki
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Patent number: 11885716Abstract: A test method for a semiconductor device comprising a substrate wafer (1), in which an element is formed and a material through which an infrared ray can be transmitted, and a package having an airtight space (7) between a cap wafer (3), which is provided opposite to the substrate wafer (1); and which includes a water applying process in which the semiconductor device is exposed to a high moisture atmosphere and a leak discrimination process in which an infrared ray from the semiconductor device is detected and a leak of the package is discriminated based on absorption of the infrared ray by water molecules.Type: GrantFiled: October 10, 2017Date of Patent: January 30, 2024Assignee: Mitsubishi Electric CorporationInventor: Hajime Sasaki
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Patent number: 11747243Abstract: In a method of producing a test-sample for a transmission electron microscope, it is so arranged that a massive body in a rectangular parallelepiped shape including a multiple quantum well active layer is cut out from a laser diode being a workpiece; thereafter, a test-sample is produced in which tilting oblique cutoff portions are formed at corner portions contiguously bordering on an upper surface of the massive body, so that surface-part active layers can be visually identified thereat; and thereafter, the test-sample is made thinner, and also an observation test-sample is cut out therefrom by taking on, as references, two surface-part active layers visually identifiable at the tilting oblique cutoff portions.Type: GrantFiled: May 25, 2018Date of Patent: September 5, 2023Assignee: Mitsubishi Electric CorporationInventor: Hajime Sasaki
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Patent number: 11499886Abstract: A test method for a semiconductor device having a package with airtight space, which is formed between a substrate wafer on which an element is formed and a cap wafer which is provided being opposite to the substrate wafer, comprises an applying water process in which the semiconductor device is exposed to high moisture atmosphere and cooled and a leak discrimination process in which power is supplied to the element which is formed on the substrate wafer and leak of the package is discriminated by detecting a sound wave which is generated by the semiconductor device.Type: GrantFiled: November 2, 2017Date of Patent: November 15, 2022Assignee: Mitsubishi Electric CorporationInventor: Hajime Sasaki
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Publication number: 20220348163Abstract: A door locking mechanism and a seat forward tilt locking mechanism are installed in a vehicle. When a user moves away from the vehicle, a door lock and a seat forward tilt lock are engaged. A signal for unlocking the door lock and a signal for releasing the seat forward tilt lock are differentiated from each other, to thereby protect the vehicle against theft.Type: ApplicationFiled: April 27, 2022Publication date: November 3, 2022Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, AISIN CORPORATIONInventors: Atsushi Shiota, Hajime Sasaki, Yuji Utoh, Hiroshi Mikoshi, Yuki Fujii
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Publication number: 20220268715Abstract: A sample (4) is created by cutting out a device on a plane (10-10). The device has a gate electrode (3) formed along a direction [2-1-10] on a plane c (0001) of a compound semiconductor (1) having a wurtzite structure. Edge dislocations having Burgers vectors of 1/3[2-1-10] and 1/3[?2110] and mixed dislocations having Burgers vectors of 1/3[2-1-13] and 1/3[?2113] are observed by making an electron beam (5) incident on the sample (4) from a direction [?1010] using a transmission electron microscope.Type: ApplicationFiled: November 1, 2019Publication date: August 25, 2022Applicant: Mitsubishi Electric CorporationInventor: Hajime SASAKI
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Patent number: 11283021Abstract: A semiconductor layer (2,3) is provided on a substrate (1). A gate electrode (4), a source electrode (5) and a drain electrode (6) are provided on the semiconductor layer (3). A strongly correlated electron system material (12) is connected between the gate electrode (4) and the source electrode (5).Type: GrantFiled: December 22, 2016Date of Patent: March 22, 2022Assignee: Mitsubishi Electric CorporationInventor: Hajime Sasaki
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Publication number: 20220009446Abstract: A biometric authentication system is configured to perform a biometric authentication operation based on biometric information of an occupant in a passenger compartment of a vehicle and is configured to permit starting of a travel driving force source in the vehicle based on a condition that biometric authentication is established in the biometric authentication operation. The biometric authentication system includes: a biometric information detecting unit configured to detect the biometric information; and a notification unit configured to issue a notification dependent on non-establishment of biometric authentication in the biometric authentication operation to the occupant. The notification unit is configured to issue the notification dependent on the non-establishment of the biometric authentication based on a condition that a brake pedal is depressed at the time of detecting the biometric information by the biometric information detecting unit when the biometric authentication is not established.Type: ApplicationFiled: July 6, 2021Publication date: January 13, 2022Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHOInventors: Yuya GOTO, Naoyuki TAKADA, Hajime SASAKI, Hirokazu ITAKURA, Takahiko ANDO, Daisuke OGAWA
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Publication number: 20210102872Abstract: In a method of producing a test-sample for a transmission electron microscope, it is so arranged that a massive body in a rectangular parallelepiped shape including a multiple quantum well active layer is cut out from a laser diode being a workpiece; thereafter, a test-sample is produced in which tilting oblique cutoff portions are formed at corner portions contiguously bordering on an upper surface of the massive body, so that surface-part active layers can be visually identified thereat; and thereafter, the test-sample is made thinner, and also an observation test-sample is cut out therefrom by taking on, as references, two surface-part active layers visually identifiable at the tilting oblique cutoff portions.Type: ApplicationFiled: May 25, 2018Publication date: April 8, 2021Applicant: Mitsubishi Electric CorporationInventor: Hajime SASAKI
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Patent number: 10957770Abstract: A semiconductor layer (2,3) is provided on a substrate (1). A gate electrode (4), a source electrode (5) and a drain electrode (6) are provided on the semiconductor layer (3). A first passivation film (7) covers the gate electrode (4) and the semiconductor layer (3). A source field plate (9) is provided on the first passivation film (7), and extends from the source electrode (5) to a space between the gate electrode (4) and the drain electrode (6). A second passivation film (10) covers the first passivation film (7) and the source field plate (9). An end portion on the drain electrode (6) side of the source field plate (9) is curved to be rounded.Type: GrantFiled: December 22, 2016Date of Patent: March 23, 2021Assignee: Mitsubishi Electric CorporationInventor: Hajime Sasaki