Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: In a shift register, which is for use in an image display apparatus of the TFT active matrix type in which a driver circuit is integrally provided on a display panel, and which is so arranged as to boost a start pulse SP to a start pulse SPO by using a level shifter, and to supply the start pulse SPO to a flip-flop F1 of a shift register section, the start pulse SP having an amplitude lower than a driving voltage and being supplied thereto, the shift register is provided with an operation control circuit for inactivating the level shifter when the first stage flip-flop F1 outputs an output signal S1 and activates the level shifter when a last stage flip-flop Fn outputs an output signal Sn. Therefore, it is possible to reduce power consumption of the level shifter during a period in which the start pulse SPO is transmitted from a flip-flop F2 to a flip-flop Fn−1.

Abstract: A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.

Abstract: A precharge circuit is composed of (a) a reference signal input section, to which at least one precharge reference potential is inputted, (b) a control signal input section, to which at least one control signal is inputted, (c) a plurality of signal delay sections for sequentially delaying an output of the control signal input section, and (d) a reference signal switching section for switching, in accordance with outputs of the signal delay sections, between a state of outputting the precharge reference potential of the reference signal input section to each of the data signal lines and a state of non-outputting the same thereto. With this arrangement, the precharge control signal is sequentially delayed within the precharge circuit by the delay circuits composed of inverter circuits or the like, so that timings at which the precharge reference potential is written in the data signal lines are dispersed.

Abstract: A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.

Abstract: A control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area is refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.

Abstract: If a clock signal ck is “H” and an input pulse signal in (first control signal) is “H”, then n-type transistors M15 and M16 are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M12 is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at “H” and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.

Abstract: A matrix type image display device has a structure in which the internal states of all of shift registers (the outputs of flip-flops included in the shift registers) in a scanning signal line drive circuit and data signal line drive circuit are made inactive by the use of an initializing signal generated by a NAND gate based on a combination of signals, which do not affect a displayed image, from a control circuit. With this structure, since the shift registers are initialized when power is supplied, it is possible to prevent an indefinite state when power is supplied. Therefore, by selectively inputting signals (such as clock signals) for controlling the shift registers, it is possible to prevent an excessive increase in the signal line load. Consequently, the operation of the image display device can be stabilized.

Abstract: A digital-to-analog converter includes a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit including switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during the precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.

Abstract: Before a potential of counter electrode is changed, a potential holding circuit fixedly holds potentials of data signal lines S during a non-selective period of scanning signal lines G. This prevents the potentials of the data signal lines S from being an undesirably large potential, which is caused by coupling capacitors between the counter electrode and each data signal line S, whereby it is possible to supply to the pixel capacitor an electric charge corresponding to a gradation to be displayed, by using the relatively low potentials of the data signal lines S. This lowers a power supply voltage of a data signal driving circuit SD, thus reducing the electric power consumption. In short, with this arrangement, a liquid crystal display device can perform an opposed AC drive for line-inversion drive, frame-inversion drive and the like, by low power supply voltage of the data signal line driving circuit SD, thereby reducing the electric power consumption.

Abstract: An active matrix display panel of the present invention is provided with (1) a plurality of row electrode lines and (2) a plurality of column electrode lines, which are arranged in a matrix, (3) a first MOS transistor provided to each pixel, having (a) a first terminal connected to each of the column electrode line, (b) a second terminal connected to a liquid crystal, and (c) a control terminal connected to each of the row electrode line, wherein an ON potential is higher than a signal potential supplied to the row electrode line, and (4) a second MOS transistor provided to each pixel, having (a) a first terminal connected to each of the row electrode line, (b) a second terminal connected to the electro-optic element, and (c) a control terminal connected to the column electrode line, wherein an ON potential is higher than a signal potential supplied to the column electrode line.

Abstract: A potential of a data signal line S during a scanning period is charged to a substantially intermediate potential of a data signal at a corresponding frame. Thus, extremely large dispersion does not occur in a potential of each pixel capacitor with respect to a potential of the data signal line S, so that it is possible to restrict dispersion of a leak current flowing via an active element of each pixel. Thus, potential variation of a pixel PIX is reduced, so that it is possible to improve display quality during a non-scanning period. That is, in an active-matrix-type liquid crystal display, when a frame frequency is reduced by setting the non-scanning period to be sufficiently larger than a scanning period while a standby image is being displayed so as to realize low power consumption, the display quality is improved.

Abstract: The scanning signal line driving circuit sequentially carries out active driving with respect to each set of a certain number of scanning signal lines which are adjacent to each other in a vertical direction, and when carrying out an actual writing with respect to a first set of a certain number of pixel lines adjacent to each other in the vertical direction, carries out pre-charging with respect to a second set of the certain number of pixel lines to which the actual writing is carried out next with a potential of a same polarity as that of the first set of the certain number of pixel lines. In this manner, it is possible to provide a matrix image display device with no irregularities in display quality and is capable of matching the apparent vertical resolution of the device to that of the image source, when using an image signal of vertical resolution lower than the maximum physical vertical resolution of the device.

Abstract: A precharge control circuit constituted by (1) a latch circuit mounted in a precharge circuit and (2) a level shifter circuit of a current drive type controlled through an output of the latch circuit is included. The precharge control circuit changes the latch circuit to an active state to cause the level shifter circuit of a current drive type to operate only during a precharge period and also during immediately preceding and succeeding periods, and outside these periods, changes the latch circuit in a non-active state and the level shifter circuit of a current drive type in an operating state to save power consumption in the level shifter circuit. This enables a low-power-consuming precharge circuit, as well as a low-power-consuming image display device with a high quality display capability, to be offered.

Abstract: An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

Abstract: A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.

Abstract: A data signal line driving circuit which sequentially forms a plurality of sampling signals and continuously samples input signals to output such input signals, in response to the plurality of sampling signals, wherein the sampling signals respectively represent sampling periods thereof which are different from each other, and a pulse width of each of the sampling signals is prescribed to be small so that rising and falling of each of the sampling signals do not overlap each other.

Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

Abstract: A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.