Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: In one embodiment of the present invention, a NAND circuit, an inverter, a plurality of transistors serve as stopping devices for stopping operation of a circuit in a manner responsive to a level of an initializing signal that is fed. If the initializing signal that is Low-level is fed into the NAND circuit, then a plurality of transistors all become OFF. This makes it possible to reduce steady current flowing across a voltage and a start signal. Steady current flowing across the voltage and a start inverted signal is also reduced. Thus, the steady current flowing through the level shifter is reduced reliably, regardless of the way of use, when necessary.

Abstract: An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

Abstract: A shift register includes control circuits CNi (i=1 through n) corresponding to respective blocks, and a level shifter LSi+1 of the next stage is controlled by one of the outputs of the shift register and one of the outputs of flip-flops Fi. With this, a level shifter of the present stage operates only for a period minimum for outputting the shift output from the present block, so that the power consumption is reduced, Furthermore, it is possible to cause the outputs SL1 through SLn not to overlap each other.

Abstract: The data signal line driving circuit of the present invention is arranged so that data signal line groups, each of which is made up of two data signal lines sequentially disposed, are connected to two video signal lines, each of which allows a two-phased video signal to be forwarded. A shift register SR, a drive switching circuit, and a waveform shaping circuit, that constitute a video signal fetching section, collect the data signal line groups via the two video signal lines as a single block. At this time, the data signal lines are respectively driven so as to fetch the video signal from the video signal lines into the data signal lines of the data signal line groups in each block. Thus, in performing multiphase development, it is possible to provide the data signal line driving circuit which can reduce power consumption in low resolution driving compared with a case of high resolution driving.

Abstract: A plurality of scanning signal lines GLn divided into groups, and each group is made up of three scanning signal lines GLnR, GLnG and GLnB, and a plurality of pixels are divided into pixel blocks, and each pixel block is made up of three pixels PR (n, m), PG (n, m) and PB (n, m) respectively connected to the scanning signal lines GLnR, GLnG and GLnB. These pixels PR (n, m), PG (n, m) and PB (n, m) are connected to a common data signal line SLm. To the scanning signal lines GLnR, GLnG, GLnB, scanning pulses are sequentially outputted to the scanning signal lines GLnR, GLnG and GLnB from shift registers SRnR, SRnG and SRnB, and video signals for R, G and B are outputted to the data signal line SLm from a driver IC by time division.

Abstract: The present invention relates to a display device and a drive method thereof. An object of the present invention is to provide a display device capable of performing multi-gray scale display with a simple circuit design, without a display image becoming coarse. A pixel circuit of a display device includes a pixel memory (50) capable of storing 1-bit data. When switching is performed from normal display to memory drive, binarized data for image display during a memory drive period is stored in the pixel memory (50). A first supply voltage (VAL) and a second supply voltage (VBL) are provided to the pixel circuit and the voltage values thereof change by a duty ratio set by a memory drive control unit (20). Upon memory drive, according to the data stored in the pixel memory (50), a voltage is applied to a liquid crystal capacitance (51) which is a display medium, based on one of the first supply voltage (VAL) and the second supply voltage (VBL), whereby image display is performed.

Abstract: A data signal line drive circuit is provided with first sampling portions, and second sampling portions operated at a lower speed. By the action of selection circuits, the first sampling portions are operated during a normal display mode, and the second sampling portions are operated during a partial display mode. To ensure a correct sampling operation, one line time and a sampling interval are rendered longer during a display period of the partial display mode than during the normal display mode. During the normal display mode, both the first sampling portions and the second sampling portions may be operated. Thus, power consumption of a liquid crystal display device during the partial display is reduced.

Abstract: The subject invention provides a drive circuit for a display apparatus, comprising: a shift register; and a pulse generation circuit for generating a drive pulse signal using an output pulse signal generated in the shift register, wherein: the pulse generation circuit forms a pulse-starting edge and a pulse-termination edge of the drive pulse signal using a rise or a fall of pulse resulting from activation of the output pulse signal. On this account, pulse generation can be performed with high accuracy in a pulse generation circuit used for a drive circuit for a display apparatus or the like.

Abstract: In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.

Abstract: A data signal line drive circuit is provided with first sampling portions, and second sampling portions operated at a lower speed. By the action of selection circuits, the first sampling portions are operated during a normal display mode, and the second sampling portions are operated during a partial display mode. To ensure a correct sampling operation, one line time and a sampling interval are rendered longer during a display period of the partial display mode than during the normal display mode. During the normal display mode, both the first sampling portions and the second sampling portions may be operated. Thus, power consumption of a liquid crystal display device during the partial display is reduced.

Abstract: In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage.

Abstract: A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n?1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.

Abstract: A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts.

Abstract: A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.

Abstract: In a structure in which a plurality of signals related to each other are supplied to a driving circuit in such a manner that at least one of the signals is supplied also to the other circuit, the present invention prevents change of phase relation between the plural signals due to difference in wiring load, without directly processing the signals with higher power consumption. The first and second clock signals SCK1 and SCK2 are supplied to the first data signal line driving circuit SD1, while the first clock signal SCK1 is also supplied to the second data signal line driving circuit SD2 in parallel. The wirings 1 and 2 for the respective signals are adjusted to have equal wiring load with a dummy wiring 2 provided in the wiring 2, for solving uneven wiring load caused by difference of leading manner, the dummy wiring 2 constituting an additional capacitor section 7, together with a liquid crystal layer and a counter electrode.

Abstract: In an embodiment, a sampling signal to each data signal line is generated by using an output signal outputted from each flip-flop, and a precharge signal by which the data signal line to which the sampling signal is to be outputted is precharged is generated by using an output signal outputted from an output terminal of the flip-flop. Further, by providing a NOR circuit, an active period of the precharge signal and an active period of the sampling signal are prevented from overlapping each other. With this, in an embodiment of a display device driving circuit, including a precharge circuit, which causes a precharge power supply to precharge signal supply lines, the number of shift registers and the size of a circuit can be reduced.

Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

Abstract: A data signal line drive circuit supplying a video signal to a pixel array performs pseudo tone gradation processing with respect to the video signal that is sent to an n number of data signal lines SL by m (<n) stages of a pseudo tone gradation processing section, and outputs the video signal processed by the pseudo tone gradation processing section identical to the data signal lines SL per m lines when sends the video signals subjected to the pseudo tone gradation processing to the data signal lines SL. By doing this, the drive circuit using the pseudo tone gradation processing is given a simple circuit structure, thereby providing an image display apparatus of a driving circuit integrated type in which the pixel array and the drive circuit are formed on a substrate.

Abstract: A driving device of a display device includes: a data signal line driving circuit, provided with a shift register having a level shifter for boosting a source clock signal so as to apply the source clock signal to a flip-flop, which causes a sampling circuit to directly sample a multi-gradation data signal based on each output from the shift register so as to output the multi-gradation data signal to each of a plurality of data signal lines; a control circuit for switching a full-screen display mode in which a whole of the display screen performs display and a partial-screen display mode in which only a part of the display screen performs time-sharing display; a data generating section for generating a constant voltage data writing signal made of a constant voltage; and a control circuit for outputting a selection signal for causing a nondisplay portion to directly sample the constant voltage data writing signal from the constant voltage data writing signal generation means so as to output the constant voltag