Patents by Inventor Hajime Watakabe
Hajime Watakabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240332427Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, a metal oxide layer over the gate insulating layer, an oxide semiconductor layer having a polycrystalline structure over the metal oxide layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode, wherein the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer, and a difference between a thickness of the first region and a thickness of the second region is 5 nm or less.Type: ApplicationFiled: March 14, 2024Publication date: October 3, 2024Applicant: Japan Display Inc.Inventors: Marina MOCHIZUKI, Masahiro WATABE, Masashi TSUBUKU, Hajime WATAKABE, Toshinari SASAKI, Takaya TAMARU, Ryo ONODERA
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Publication number: 20240332429Abstract: A semiconductor device comprises a metal oxide layer on an insulating surface; an oxide semiconductor layer on the metal oxide layer; a gate insulating layer on the oxide semiconductor layer; and a gate wiring on the gate insulating layer. The metal oxide layer has a first region overlapping the gate wiring and the oxide semiconductor layer, a second region overlapping the oxide semiconductor layer and not overlapping the gate wiring, and a third region overlapping the gate wiring and not overlapping the oxide semiconductor layer.Type: ApplicationFiled: March 27, 2024Publication date: October 3, 2024Applicant: Japan Display Inc.Inventors: Masahiro WATABE, Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Marina MOCHIZUKI, Takaya TAMARU, Ryo ONODERA
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Patent number: 12108627Abstract: A display device includes a first transistor having a first semiconductor layer, in which a first source region includes a first region in contact with a first source electrode, and a first drain region includes a second region in contact with a first drain electrode. The first source and drain regions, the first region, and the second region each include a first impurity element. In a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region. A method of manufacturing a display device includes forming a first gate electrode and a light shielding layer on a first insulating layer, and forming a second semiconductor layer on the light shielding layer.Type: GrantFiled: November 23, 2021Date of Patent: October 1, 2024Assignee: JAPAN DISPLAY INC.Inventors: Akihiro Hanada, Kentaro Miura, Hajime Watakabe, Ryo Onodera
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Publication number: 20240312999Abstract: A semiconductor device includes a first transistor on a substrate and a second transistor on the first transistor. The first transistor includes a first gate electrode on the substrate, a first insulating film on the first gate electrode, a first oxide semiconductor layer on the first insulating film, having a region overlapping the first gate electrode, and having a polycrystalline structure, a second insulating film on the first oxide semiconductor layer, and a second gate electrode on the second insulating film. The second transistor includes a third gate electrode on the second insulating film, a third insulating film on the third gate electrode, a second oxide semiconductor layer on the third insulating film and having a region overlapping the third gate electrode, a fourth insulating film on the second oxide semiconductor layer, and a fourth gate electrode on the fourth insulating film.Type: ApplicationFiled: February 27, 2024Publication date: September 19, 2024Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU, Marina MOCHIZUKI, Ryo ONODERA
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Patent number: 12085823Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.Type: GrantFiled: November 16, 2022Date of Patent: September 10, 2024Assignee: JAPAN DISPLAY INC.Inventors: Toshihide Jinnai, Hajime Watakabe, Akihiro Hanada, Ryo Onodera, Isao Suzumura
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Publication number: 20240290861Abstract: A semiconductor device according to an embodiment includes: a first gate electrode; a first insulating layer on the first gate electrode; an oxide semiconductor layer on the first insulating layer; a second insulating layer on the oxide semiconductor layer; and a second gate electrode on the second insulating layer. The first insulating layer includes a first layer including silicon and nitrogen, a second layer including silicon and oxygen, and a third layer including aluminum and oxygen. A thickness of the first layer is 10 nm or more and 190 nm or less. A thickness of the second layer is 10 nm or more and 100 nm or less. A total thickness of the first layer and the second layer is 200 nm or less. A thickness of the third layer 1 nm or more and 10 nm or less.Type: ApplicationFiled: February 7, 2024Publication date: August 29, 2024Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU, Marina MOCHIZUKI, Ryo ONODERA, Masahiro WATABE
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Publication number: 20240288739Abstract: An electronic device comprises a first stacked structure including a first oxide semiconductor layer having a polycrystalline structure, a first insulating layer on the first oxide semiconductor layer, and a first conductive layer overlapping the first oxide semiconductor layer via the first insulating layer; and a second stacked structure including a second oxide semiconductor layer composed of the same layer as the first oxide semiconductor layer, the first insulating layer on the second oxide semiconductor layer, and a second conductive layer overlapping the second oxide semiconductor layer via the first insulating layer and composed of the same layer as the first conductive layer. A portion of the first oxide semiconductor layer not overlapping the first conductive layer contains an impurity element, and the second oxide semiconductor layer does not contain the impurity element.Type: ApplicationFiled: February 6, 2024Publication date: August 29, 2024Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU, Marina MOCHIZUKI, Ryo ONODERA
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Patent number: 12072595Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.Type: GrantFiled: November 7, 2023Date of Patent: August 27, 2024Assignee: Japan Display Inc.Inventors: Akihiro Hanada, Toshihide Jinnai, Isao Suzumura, Hajime Watakabe, Ryo Onodera
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Publication number: 20240250091Abstract: A semiconductor device includes an oxide semiconductor layer including a polycrystalline structure, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer connected to the oxide semiconductor layer, and a second transparent conductive layer arranged in the same layer as the first transparent conductive layer and separated from the first transparent conductive layer, wherein crystallizability of the first transparent conductive layer is different from crystallizability of the second transparent conductive layer.Type: ApplicationFiled: January 12, 2024Publication date: July 25, 2024Applicant: Japan Display Inc.Inventors: Masahiro WATABE, Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Marina MOCHIZUKI, Takaya TAMARU, Ryo ONODERA
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Publication number: 20240178325Abstract: A semiconductor device includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on and in contact with the oxide semiconductor layer, and a gate electrode on the gate insulating layer. The oxide semiconductor layer includes a channel region overlapping the gate electrode, and source and drain regions that do not overlap the gate electrode. At an interface between the source and drain regions and the gate insulating layer, a concentration of an impurity on a surface of at least one of the source and drain regions is greater than or equal to 1×1019 cm?3.Type: ApplicationFiled: November 27, 2023Publication date: May 30, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU, Marina MOCHIZUKI, Ryo ONODERA
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Publication number: 20240176196Abstract: A display device includes a plurality of pixel electrodes each connected to a semiconductor device, a plurality of common electrodes each disposed opposite to a part of the plurality of pixel electrodes, and a plurality of common wirings each connected to the plurality of common electrodes. The semiconductor device includes an oxide semiconductor layer having a polycrystalline structure, and at least a part of each common wiring is composed of the oxide semiconductor layer. Each common electrode may be located across a plurality of pixel electrodes.Type: ApplicationFiled: November 14, 2023Publication date: May 30, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
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Publication number: 20240128273Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Inventors: Hajime WATAKABE, Toshihide JINNAI, Ryo ONODERA, Akihiro HANADA
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Publication number: 20240113227Abstract: A method for manufacturing semiconductor device according to an embodiment includes: forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the metal oxide layer is formed above the gate insulating layer; removing the metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.Type: ApplicationFiled: September 28, 2023Publication date: April 4, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Akihiro HANADA, Takaya TAMARU
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Publication number: 20240113228Abstract: A semiconductor device according to an embodiment includes: an oxide insulating layer; an oxide semiconductor layer; a gate electrode; a gate insulating layer; and a first insulating layer, wherein the semiconductor device is divided into a first to a third regions, a thickness of the gate insulating layer in the first region is 200 nm or more, the gate electrode contacts the first insulating layer in the first region, the oxide semiconductor layer contacts the first insulating layer in the second region, an amount of impurities contained in the oxide semiconductor layer in the second region is greater than an amount of impurities contained in the oxide semiconductor layer in the first region, and an amount of impurities contained in the oxide insulating layer in the third region is greater than an amount of impurities contained in the oxide insulating layer in the second region.Type: ApplicationFiled: October 3, 2023Publication date: April 4, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Akihiro HANADA, Takaya TAMARU
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Publication number: 20240105819Abstract: A method for manufacturing a semiconductor device includes depositing a first metal oxide film with aluminum as a major component on a substrate, depositing an amorphous oxide semiconductor film on the first metal oxide film under an oxygen partial pressure of 3% to 5%, processing the oxide semiconductor film into a patterned oxide semiconductor layer, crystallizing the oxide semiconductor layer by performing a first heat treatment on the patterned oxide semiconductor layer, processing the first metal oxide film using the crystallized oxide semiconductor layer as a mask, depositing a gate insulating film on the oxide semiconductor layer, and forming a gate electrode on the gate insulating film, wherein a thickness of the oxide semiconductor film is more than 10 nm and 30 nm or less.Type: ApplicationFiled: September 26, 2023Publication date: March 28, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
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Patent number: 11942484Abstract: A semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.Type: GrantFiled: July 28, 2022Date of Patent: March 26, 2024Assignee: Japan Display Inc.Inventors: Akihiro Hanada, Hajime Watakabe, Kazufumi Watabe
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Publication number: 20240097043Abstract: A semiconductor device according to an embodiment of the present invention includes an oxide insulating layer, an oxide semiconductor layer, a gate insulating layer, a gate electrode, and a protective insulating layer. The gate insulating layer includes a first region overlapping the gate electrode and a second region not overlapping the gate electrode. The second region is in contact with the protective insulating layer. The oxide insulating layer includes a third region overlapping the gate electrode and a fourth region not overlapping the gate electrode and the oxide semiconductor layer. The fourth region is in contact with the gate insulating layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. Each of the source region, the drain region, and the second region contains an impurity. A hydrogen concentration of the second region is greater than a hydrogen concentration of the first region.Type: ApplicationFiled: August 28, 2023Publication date: March 21, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takay TAMARU
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Publication number: 20240088192Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Akihiro HANADA, Marina MOCHIZUKI, Ryo ONODERA, Fumiya KIMURA, Isao SUZUMURA
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Publication number: 20240088302Abstract: A semiconductor device according to an embodiment includes: a substrate; a metal oxide layer arranged above the substrate and having aluminum as the main component of the metal oxide layer; an oxide semiconductor layer arranged above the metal oxide layer; a gate electrode facing the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein a thickness of the metal oxide layer is 1 nm or more and 4 nm or less.Type: ApplicationFiled: September 12, 2023Publication date: March 14, 2024Applicant: Japan Display Inc.Inventors: Takaya TAMARU, Masashi TSUBUKU, Hajime WATAKABE, Toshinari SASAKI
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Publication number: 20240069400Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Applicant: Japan Display Inc.Inventors: Akihiro HANADA, Toshihide JINNAI, Isao SUZUMURA, Hajime WATAKABE, Ryo ONODERA