Patents by Inventor Hamid Azimi

Hamid Azimi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10306760
    Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Publication number: 20170231092
    Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.
    Type: Application
    Filed: April 25, 2017
    Publication date: August 10, 2017
    Inventors: Yonggang Li, Islam SALAMA, Charan GURUMURTHY, Hamid AZIMI
  • Patent number: 9648733
    Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Publication number: 20130242498
    Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.
    Type: Application
    Filed: April 11, 2013
    Publication date: September 19, 2013
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Patent number: 8440916
    Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Publication number: 20110254124
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 20, 2011
    Inventors: Ravi K. Nalla, John Guzek, Javier Soto Gonzalez, Drew Delaney, Hamid Azimi
  • Patent number: 7985622
    Abstract: A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: July 26, 2011
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Publication number: 20100044862
    Abstract: A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Inventors: Ravi Nalla, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Publication number: 20090002958
    Abstract: A method of fabricating a substrate core structure comprises, providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Patent number: 7413936
    Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
  • Publication number: 20080096323
    Abstract: A system may include a plurality of pliant conductive elements, a first end of one of the plurality of pliant conductive elements to be electrically coupled to a first electrical contact of an integrated circuit substrate and a second end of the one of the plurality of pliant conductive elements to be electrically coupled to a second electrical contact of an integrated circuit die.
    Type: Application
    Filed: December 14, 2007
    Publication date: April 24, 2008
    Inventors: Gilroy Vandentop, Hamid Azimi
  • Patent number: 7042077
    Abstract: A system may include a coreless substrate, a layer of material attached to the substrate, the layer of material having a lower elastic modulus than the substrate, an interposer coupled to the layer of material, and a capacitive layer coupled to the interposer.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Michael J. Walk, Hamid Azimi, John S. Guzek, Charan K. Gurumurthy
  • Publication number: 20060060946
    Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.
    Type: Application
    Filed: November 9, 2005
    Publication date: March 23, 2006
    Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
  • Patent number: 7005727
    Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
  • Publication number: 20050230841
    Abstract: A system may include a coreless substrate, a layer of material attached to the substrate, the layer of material having a lower elastic modulus than the substrate, an interposer coupled to the layer of material, and a capacitive layer coupled to the interposer.
    Type: Application
    Filed: April 15, 2004
    Publication date: October 20, 2005
    Inventors: Michael Walk, Hamid Azimi, John Guzek, Charan Gurumurthy
  • Publication number: 20050063164
    Abstract: A system may include a plurality of pliant conductive elements, a first end of one of the plurality of pliant conductive elements to be electrically coupled to a first electrical contact of an integrated circuit substrate and a second end of the one of the plurality of pliant conductive elements to be electrically coupled to a second electrical contact of an integrated circuit die.
    Type: Application
    Filed: September 22, 2003
    Publication date: March 24, 2005
    Inventors: Gilroy Vandentop, Hamid Azimi
  • Patent number: 6858475
    Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: February 22, 2005
    Assignee: Intel Corporation
    Inventors: Charan K. Gurumurthy, Hamid Azimi, Arthur K. Lin
  • Publication number: 20040266070
    Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Charan K. Gurumurthy, Hamid Azimi, Arthur K. Lin
  • Publication number: 20040107569
    Abstract: Apparatus and methods are provided for a rigid metal core carrier substrate. The metal core increases the modulus of elasticity of the carrier substrate to greater than 20 GPa to better resist bending loads and stresses encountered during assembly, testing and consumer handling. The carrier substrate negates the need to provide external stiffening members resulting in a microelectronic package of reduced size and complexity. The coefficient of thermal expansion of the carrier substrate can be adapted to more closely match that of the microelectronic die, providing a device more resistant to thermally-induced stresses. In one embodiment of the method in accordance with the invention, a metal sheet having a thickness in the range including 200-500 &mgr;m and a flexural modulus of elasticity of at least 20 GPa is laminated on both sides with dielectric and conductive materials using standard processing technologies to create a carrier substrate.
    Type: Application
    Filed: December 5, 2002
    Publication date: June 10, 2004
    Inventors: John Guzek, Hamid Azimi, Dustin Wood
  • Publication number: 20040004232
    Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.
    Type: Application
    Filed: September 3, 2002
    Publication date: January 8, 2004
    Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana