Patents by Inventor Hamid Azimi

Hamid Azimi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050063164
    Abstract: A system may include a plurality of pliant conductive elements, a first end of one of the plurality of pliant conductive elements to be electrically coupled to a first electrical contact of an integrated circuit substrate and a second end of the one of the plurality of pliant conductive elements to be electrically coupled to a second electrical contact of an integrated circuit die.
    Type: Application
    Filed: September 22, 2003
    Publication date: March 24, 2005
    Inventors: Gilroy Vandentop, Hamid Azimi
  • Patent number: 6858475
    Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: February 22, 2005
    Assignee: Intel Corporation
    Inventors: Charan K. Gurumurthy, Hamid Azimi, Arthur K. Lin
  • Publication number: 20040266070
    Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Charan K. Gurumurthy, Hamid Azimi, Arthur K. Lin
  • Publication number: 20040107569
    Abstract: Apparatus and methods are provided for a rigid metal core carrier substrate. The metal core increases the modulus of elasticity of the carrier substrate to greater than 20 GPa to better resist bending loads and stresses encountered during assembly, testing and consumer handling. The carrier substrate negates the need to provide external stiffening members resulting in a microelectronic package of reduced size and complexity. The coefficient of thermal expansion of the carrier substrate can be adapted to more closely match that of the microelectronic die, providing a device more resistant to thermally-induced stresses. In one embodiment of the method in accordance with the invention, a metal sheet having a thickness in the range including 200-500 &mgr;m and a flexural modulus of elasticity of at least 20 GPa is laminated on both sides with dielectric and conductive materials using standard processing technologies to create a carrier substrate.
    Type: Application
    Filed: December 5, 2002
    Publication date: June 10, 2004
    Inventors: John Guzek, Hamid Azimi, Dustin Wood
  • Publication number: 20040004232
    Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.
    Type: Application
    Filed: September 3, 2002
    Publication date: January 8, 2004
    Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
  • Patent number: 6600233
    Abstract: An integrated circuit package fabricated by attaching a surface mount pin to a pin pad on a substrate using a Sn—Sb solder composition, where the quantity of Sb is in a range from 4 percent to 10 percent by weight. The Sn—Sb composition has a melting point above the melting point of commonly-used Sn—Pb solders. Thus, after the pins are surface mounted to the substrate, the pin integrity is not later compromised by assembly steps that reheat the substrate to a temperature sufficient to reflow the Sn—Pb solder. In one embodiment, the surface mount pins are attached to the bottom surface of an organic substrate using the Sn—Sb composition, and a flip-chip is attached to the top surface using Sn—Pb solder bumps. An integrated circuit package includes the substrate, the surface mount pins, and the Sn—Sb solder composition on the bonding surfaces of the pins.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: July 29, 2003
    Assignee: Intel Corporation
    Inventors: Hwai-Peng Yeoh, Hamid Azimi, Amir Nur Rashid Wagiman, Mirng-Ji Lii
  • Publication number: 20020125583
    Abstract: An integrated circuit package fabricated by attaching a surface mount pin to a pin pad on a substrate using a Sn—Sb solder composition, where the quantity of Sb is in a range from 4 percent to 10 percent by weight. The Sn—Sb composition has a melting point above the melting point of commonly-used Sn—Pb solders. Thus, after the pins are surface mounted to the substrate, the pin integrity is not later compromised by assembly steps that reheat the substrate to a temperature sufficient to reflow the Sn—Pb solder. In one embodiment, the surface mount pins are attached to the bottom surface of an organic substrate using the Sn—Sb composition, and a flip-chip is attached to the top surface using Sn—Pb solder bumps. An integrated circuit package includes the substrate, the surface mount pins, and the Sn—Sb solder composition on the bonding surfaces of the pins.
    Type: Application
    Filed: May 8, 2002
    Publication date: September 12, 2002
    Applicant: Intel Corporation
    Inventors: Hwai-Peng Yeoh, Hamid Azimi, Amir Nur Rashid Wagiman, Mirng-Ji Lii
  • Patent number: 6430058
    Abstract: An integrated circuit package is provided that includes a multi-layer organic substrate. The substrate has conductive vias provided between isolated conductive layers. The vias are formed using a laser to cut through a dielectric layer separating the conductive layers. External interconnects in the form of T-shaped pins are soldered to the substrate of the integrated circuit package. An integrated circuit can be attached to the substrate using a flip-chip technique.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: August 6, 2002
    Assignee: Intel Corporation
    Inventors: Bob Sankman, Hamid Azimi
  • Patent number: 6413849
    Abstract: A method for attaching a surface mount pin to a pin pad on a substrate uses a Sn—Sb solder composition, where the quantity of Sb is in a range from 4 percent to 10 percent by weight. The Sn—Sb composition has a melting point above the melting point of commonly-used Sn—Pb solders. Thus, after the pins are surface mounted to the substrate, the pin integrity is not later compromised by assembly steps that reheat the substrate to a temperature sufficient to reflow the Sn—Pb solder. In one embodiment, the surface mount pins are attached to the bottom surface of an organic substrate using the Sn—Sb composition, and a flip-chip is attached to the top surface using Sn—Pb solder bumps. An integrated circuit package includes the substrate, the surface mount pins, and the Sn—Sb solder composition on the bonding surfaces of the pins.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: July 2, 2002
    Assignee: Intel Corporation
    Inventors: Hwai-Peng Yeoh, Hamid Azimi, Amir Nur Rashid Wagiman, Mirng-Ji Lii