Abstract: A highly intelligent DSP load management system is described herein for enhancing the processing capabilities of an SOC device. The DSP load management system enables parallel processing of data at high frequency and distributes, reads and writes data to several CPUs and/or DSPs in the same clock cycle. In addition, the DSP load management system provides forward looking real-time evaluation of arriving data and diverts tasks from one DSP to another, with short or zero latency. The DSP load management system is interfaced between one or more CPUs, one or more DSPs and/or a memory management system for enabling parallel processing of data at high frequency.

Abstract: A highly intelligent programmable multi-tasking memory management system manages memory requests associated with a system on chip (SOC) device. The memory management system includes a routing controller or central processing unit (RCPU) that is used for routing/switching stream data between communication cores and digital signal processors with minimum reliance and demand on a main or virtual central processing unit (VCPU) residing on a system bus. Tasks are partitioned between the VCPU and the RCPU within the SOC architecture for communication applications. The VCPU performs system/application tasks while the RCPU simultaneously performs multiple memory routing/switching tasks and multiple concurrent memory access connections. The memory management system also enables other processors and communication cores to update their internal data once new data is written in the memory system.

Abstract: The present invention relates to a system and method for canceling echoes from telecommunications networks by providing a system on chip having a line echo canceller and tone detector. Unlike conventional echo cancellers, the present invention uses a chip to cancel echoes that are generated in the network. In addition, the echo canceller of the present invention performs line echo cancellation, far end echo cancellation, acoustic and hybrid echo cancellation, noise processing, fax/data tone detection, DTMF, and digital timing. The present invention uses multiplexed analog delay lines, analog multipliers and adders/subtractors to perform and accelerate echo canceling, thereby enhancing channel density and optimizing scalable design of the chip and avoiding expensive chip with large on-chip logic and memory that is typically required in digital echo cancellers.

Abstract: A low light level detection and imaging device including a photon sensing and counting device for image detection that is capable of detecting/imaging low photon flux levels over a wide spectral range using either image tube or solid state readout. The sensing and counting is composed of a detector stack having several photoconductive layers, at least one layer of the stack being an amorphous Selenium layer that is capable of high gain avalanche multiplication. The stack further includes an amorphous Silicon layer deposited on the amorphous Selenium layer to absorb infrared and ultraviolet radiation to enhance responsivity in the red and near-IR region, whereas the purpose of the amorphous Selenium layer is to provide high responsivity in the blue region and also to provide avalanche gain or multiplication of the photo generated carriers in both the amorphous Silicon or Selenium layers.

Abstract: A memory efficient system of storing color correction information for liquid crystal tuning filters when used with electronic imaging cameras to produce color images, which color correction information is stored with maximum possible gain to optimize accuracy preparatory to compression. The system bins the color correction image, for example, from a 4K.times.4K CCD sensor into a 500.times.500 or 1K.times.1K file, and then applies the JPEG and/or wavelet compression algorithm with a default configuration and/or a custom quantization table that emphasizes low frequency changes with more bits than high frequency changes with less bits. At the end of the compression, the compressed R, G, B files and an n-point correction executable algorithm are stored on floppy disk or CD ROM and are used to automatically take control of image enhancement when invoked by the photographer.

Abstract: A broad band solid state image sensor responsive to up to and beyond 1 .mu.m cutoff wavelength for use in a camera capable of imaging under very low light level conditions with good modulation transfer efficiency resulting in high resolution. The high sensitivity at low light level is achieved by an image sensor combination of a photoconductor with high avalanche detection gain, a silicon detector with very high gain pixel level amplifiers and noise suppression circuits. A high gain avalanche rushing photoconductor (HARP) sensor device is connected to an amplified metal-oxide silicon (AMOS) device and a low-noise read-out device. The high sensitivity image sensor is fabricated by depositing an amorphous Selenium photoconductive layer on the top of a Silicon junction diode or a Palladium Silicide, (Pd2Si) Schottky barrier diode that is connected to the AMOS pixel amplifier circuits to form two story circuit.

Abstract: Charge coupled device X-ray sensor and camera capable of imaging with high modulation transfer function for high resolution. The high resolution is achieved by a method of simultaneously measuring the modulation transfer functions of x-ray and visible images while imaging the target or the scene. Then, by using the point spread function and measured MTFs at various spatial frequencies to calculating spatial frequency dependent correction table or correction parameters. This correction is applied to the raw image of the target inside a workstation using a software embodiment of the correction algorithm. The high precision, multi-spatial frequency patterns that are used in x-ray image correction are provided on the sensor, the scintillator screen and the fiber optic face plate of a sensor device to enable the user of the workstation to measure the modulation transfer functions (contrast transfer function) in the horizontal, vertical and in oblique orientations at several spatial frequencies.

Abstract: An image sensor device capable of snap shot color applications comprising an array of image registers for converting the light from successive image frame exposures into indicative charge packets, and an array of light-shielded storage registers interspersed in regular displacements among the array of image registers for receiving the transfer of the charge packets from adjacent image registers over multiple image frame exposures, whereby, for example, red, green, and blue color image frames can be rapidly acquired upon the opening of a flash exposure shutter, and very rapidly transferred in parallel into the storage registers from which the three frames can be read out as a color image when the shutter is closed.

Abstract: A programmable analog N.times.M switching network that includes a charge-coupled-device (CCD) multiplexer switch means having a plurality of N input leads. The input leads contain signals from typical devices such as video cassette recorders, televisions, video cameras, cable TV telephones or the like. The CCD multiplexer switch means also includes a plurality of M output leads that provide signals to other typical devices which also may be video cassette recorders, televisions, telephones, etc. A programmable read-only memory (PROM) clock generator provides signals to CCD gates in the CCD multiplexer switch means to enable the multiplexer switch means 10 to selectively connect the input signals and leads to the output leads. The programmable PROM is controlled by means of programming request means which may be a computer or an operator console.

Abstract: The present invention is an integrated imaging device capable of providing preprocessed images. An image processing unit receives command and control signals to perform selected image or signal processing operations before outputting the image. The imaging array uses either a full or linear array of photodetectors to capture an image of pixel charges. A plurality of pixel storage registers store the pixel charges and allow internal signal processing before transferring the image via an output register to an outside receiving device. A transfer register allows for transferring the pixel charges to a frame storage register. A dump drain permits is included for dumping unwanted data before transfer to the frame storage register. The array uses Si detectors or platinum silicide (PtSi) Schottky barrier detectors (or both) and is capable of both infrared and visual imaging.

Abstract: A multi-function imaging and tracking device is disclosed. A first Schottky diode array lying in a first plane performs a tracking and acquisition function. A second Schottky diode array lying in a second plane performs an imaging function. The first array is a low resolution, high-speed array while the second array is a high resolution, low-speed array. The second array having an operational parameter to be adjusted by the first array.

Abstract: A plurality of CCD imagers have their respective image registers arranged in side-by-side alignment respectively to receive contiguous portions of an image. The CCD imagers have respective field storage registers disposed on both sides of the arrayed image registers. The CCD imagers are operated with the direction of TDI operation relative to the positioning of the imager chosen such that a combined TDI operation in one direction is obtained for the plurality of CCD imagers.

Abstract: A CCD storage register for storing an area array of picture elements in a solid-state imager comprises a first set of charge transfer channels arranged in a parallel array with intervening spaces. Respective ones of a second set of charge transfer channels are located in spaces adjacent to the second set of charge transfer channels. Charge transfer stages in adjacent charge transfer channels in said first and second sets of charge transfer channels have corresponding charge storage sites between which connections for charge transfer can be made selectively. This allows shift and add procedures to be carried forward in the CCD storage register. The shift and add capability allows time-delay-integration procedures and true line interlacing procedures, as examples, to be carried forward in the CCD storage register.

Abstract: A CCD storage register for storing an area array of picture elements in a solid-state imager comprises a plurality of charge transfer channels in a parallel array. Charge transfer stages in those channels have corresponding charge storage sites facilitating charge transfer from each charge transfer stage to its corresponding charge storage site. Provisions are also made for charge transfer from each charge storage site back to its corresponding charge transfer stage or to a subsequent charge transfer stage. Such charge transfer schemes allows shift and add procedures to be carried forward in the CCD storage register. The shift and add capability allows time-delay-integration procedures and true line interlacing procedures, as examples, to be carried forward in the CCD storage register.

Abstract: Parallelled charge transfer channels have multiple-phase-clocked gate electrodes overspanning them in one of a number of arrangements conditioning the transfer of charge packets in opposing directions in adjacent charge transfer channels. Three-phase, four-phase, five-phase and six-phase clocking arrangements constructed in three layers of polysilicon embody the invention.

Abstract: A charge-coupled device (CCD) image sensor includes in a substrate of single crystalline silicon of one conductivity type an array of a plurality of spaced, parallel channel regions of the opposite conductivity type extending along one major surface of the substrate. A plurality of parallel conductive gates are over the one major surface of the substrate and extend transversely across the channel regions. The outermost channel regions of the array are positioned adjacent edges of the substrate so that a plurality of the image sensors can be mounted in edge-to-edge relation with the channel regions of the various sensors being close together. The sensor includes passivating means between each outermost channel region and the adjacent edge to prevent charge carriers generated by the edge from being injected into the outermost channel region.

Abstract: CCD imagers with a novel replicated-line-imager architecture are abutted to form an extended line sensor. The sensor is preceded by optics having a slit aperture and having an optical beam splitter or astigmatic lens for projecting multiple line images through an optical color-discriminating stripe filter to the CCD imagers. A very high resolution camera suitable for use in a satellite, for example, is thus provided. The replicated-line architecture of the imager comprises an area-array CCD, successive rows of which are illuminated by replications of the same line segment, as transmitted by respective color filter stripes. The charge packets formed by accumulation of photoresponsive charge in the area-array CCD are read out row by row. Each successive row of charge packets is then converted from parallel to serial format in a CCD line register and its amplitude sensed to generate a line of output signal.

Abstract: There is disclosed herein a method of making a device made up of at least two separate parts each of which is formed of a patterned array with the parts being mounted one on the other, with the patterned arrays of the parts being aligned, such as a CCD imager having a color filter thereon. The two parts are made on separate substrates with a first alignment key being formed on each substrate. The first alignment keys are formed by photolithography using the same mask to form the first alignment keys on each substrate. The various features of each of the parts are then formed on each substrate with each feature being formed by a photolithographic step using a mask which is aligned to a first alignment key so as to align all the features. A second alignment key is formed on each substrate and is positioned on each substrate in the same relationship with a first alignment key.

Abstract: The present invention relates to a frame transfer charge-coupled device imager which includes along a major surface of a substrate of semiconductor material a photosensing array A-register, a temporary storage B-register and an output C-register. The C-register includes a channel region in the substrate and extending along the substrate surface across the ends of and substantially perpendicular to spaced, parallel channel regions of the B-register. The C-register also includes a plurality of parallel, conductive gates extending transversely across the C-register channel region substantially parallel to the B-register channel regions. The gates include a plurality of sets with a plurality of gates per set. One gate of each set extends to a conductive termination which extends along one side of the C-register channel region over the B-register and the gates of the other sets extend to conductive terminations which are along the side of the C-register channel region opposite the B-register.

Abstract: An array of infra-red (IR) detectors for a CCD image sensor includes a plurality of spaced areas of a conductive material at the surface of a substrate of semiconductor material of one conductivity type with each conductive area forming a Schottky-barrier diode with the substrate to form the IR detectors. Each detector includes a high conductivity contact region within the substrate. Between the detector area is a guard band which consists of a region of a conductivity type opposite to that of the substrate within the substrate and around said detector area. The guard band is spaced from the contact regions and each conductive area overlaps a portion of its adjacent guard band.