Patents by Inventor Han Chang

Han Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190259849
    Abstract: A method includes receiving a device having a substrate and a first dielectric layer surrounding a gate trench. The method further includes depositing a gate dielectric layer and a gate work function (WF) layer in the gate trench and forming a hard mask (HM) layer in a space in the gate trench and surrounded by the gate WF layer. The method further includes recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer. After the recessing of the gate WF layer, the method further includes removing the HM layer in the gate trench and depositing a metal layer in the gate trench. The metal layer is in physical contact with a sidewall surface of the gate WF layer that is deposited before the HM layer is formed.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Chih-Han Lin, Che-Cheng Chang, Horng-Huei Tseng
  • Publication number: 20190259924
    Abstract: A semiconductor package structure is disclosed. The package structure includes a first substrate, a second substrate on which the first substrate is disposed, and a semiconductor chip which is disposed on the first substrate. The two substrates can include two notches or two solder receiving portions. Therefore, when the package structure is disposed on the printed circuit board (PCB), the package structure will protrude less on the surface of the printed circuit board (PCB); or, the solders on the printed circuit board (PCB) will not be shifted by the package structure.
    Type: Application
    Filed: August 27, 2018
    Publication date: August 22, 2019
    Applicant: Everlight Electronics Co., Ltd.
    Inventors: Chih-Ming Ho, Chun-Chih Liang, Ding-Hwa Cherng, Kuang-Mao Lu, Wen-Chueh Lo, Hao-Yu Yang, Chieh-Yu Kang, Han-Chang Pan
  • Patent number: 10386934
    Abstract: A gesture operation method based on depth values and the system thereof are revealed. A stereoscopic-image camera module acquires a first stereoscopic image. Then an algorithm is performed to judge if the first stereoscopic image includes a triggering gesture. Then the stereoscopic-image camera module acquires a second stereoscopic image. Another algorithm is performed to judge if the second stereoscopic image includes a command gesture for performing the corresponding operation of the command gesture.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 20, 2019
    Assignee: Metal Industries Research & Development Centre
    Inventors: Jinn-Feng Jiang, Shih-Chun Hsu, Tsu-Kun Chang, Tsung-Han Lee, Hung-Yuan Wei
  • Publication number: 20190248868
    Abstract: The present invention provides nucleic acids encoding B7-related factors that modulate the activation of immune or inflammatory response cells, such as T-cells. Also provided are expression vectors and fusion constructs comprising nucleic acids encoding B7-related polypeptides, including BSL1, BSL2, and BSL3. The present invention further provides isolated B7-related polypeptides, isolated fusion proteins comprising B7-related polypeptides, and antibodies that are specifically reactive with B7-related polypeptides, or portions thereof. In addition, the present invention provides assays utilizing B7-related nucleic acids, polypeptides, or peptides. The present invention further provides compositions of B7-related nucleic acids, polypeptides, fusion proteins, or antibodies that are useful for the immunomodulation of a human or animal subject.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 15, 2019
    Inventors: Glen Eugene Mikesell, Han Chang, Robert James Peach
  • Publication number: 20190254191
    Abstract: A backflow prevention device includes at least one channeled body and at least one moving part. The at least one channeled body includes at least one first opening and at least one second opening. Each of the at least one channeled body gradually enlarges from each of the at least one first opening to each of the at least one second opening. Each of the at least one moving part is movably disposed in each of the at least one channeled body. A size of the moving part is less than a size of the second opening. When an airflow back flows from the second opening to the first opening, the airflow drives the moving part to enable the moving part to block the first opening. A server system is also disclosed.
    Type: Application
    Filed: May 15, 2018
    Publication date: August 15, 2019
    Applicant: Wistron Corporation
    Inventors: Tsung-Han Chang, Hua Chen
  • Publication number: 20190253676
    Abstract: An illumination system includes an exciting light source module, a dichroic element, a wavelength-converting element, a light homogenizing element and a lens array. The exciting light source module includes a plurality of exciting light sources, each for providing an exciting beam. The dichroic element allows the exciting beam to be transmitted to the wavelength-converting element. The wavelength-converting element converts the exciting beam into a converted beam and reflects the converted beam to the dichroic element, and the dichroic element transmits the converted beam to the light homogenizing element. The light homogenizing element has a light incident end. The lens array includes a plurality of lens units, and a long side of each of the lens units is parallel to a long side of the light incident end when being projected along the transmission path of the converted beam to the light incident end.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 15, 2019
    Inventors: CHIH-HSIEN TSAI, HSIN-YUEH CHANG, YI-HSUANG WENG, JO-HAN HSU, CHI-TANG HSIEH
  • Publication number: 20190252896
    Abstract: A charging circuit includes a power conversion circuit, an inductor, and at least one conversion capacitor. The power conversion circuit includes a conversion switch circuit and a conversion control circuit. The conversion switch circuit includes an upper switch, a lower switch, and at least one auxiliary switch. In a switching conversion mode, the conversion control circuit operates the conversion switch circuit to switch the inductor to plural voltage levels repetitively for converting an input power to a charging power to charge a battery by switching power conversion. In a capacitive conversion mode, the conversion control circuit operates the conversion switch circuit to switch the conversion capacitor between two of voltage division nodes periodically for converting the input power to the charging power by capacitive power conversion.
    Type: Application
    Filed: October 22, 2018
    Publication date: August 15, 2019
    Inventors: Wei-Jen Huang, Tsung-Han Lee, Shun-Yu Huang, Chun-Kai Chang
  • Patent number: 10377714
    Abstract: A trans-isomeric compound of formula (I) below or a pharmaceutically acceptable salt thereof: in which R1 is C1-C5 alkyl or C3-C5 cycloalkyl and the trans-isomeric compound has a trans:cis ratio of at least 70:30. Further disclosed is a method for preparing the trans-isomeric compound.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: August 13, 2019
    Assignee: TaiGen Biotechnology Co., Ltd.
    Inventors: Shan-Yen Chou, Wen-Chang Chen, Chi-Feng Yen, Han-Pei Hsu, Ming-Chu Hsu, Chu-Chung Lin
  • Publication number: 20190244957
    Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Publication number: 20190244864
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang
  • Publication number: 20190244863
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10374003
    Abstract: A semiconductor light emitting device includes a plurality of light emitting cells having first and second surface opposing each other, the plurality of light emitting cells including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer therebetween, an insulating layer on the second surface of the plurality of light emitting cells and having first and second openings defining a first contact region of the first conductivity-type semiconductor layer and a second contact region of the second conductivity-type semiconductor layer, respectively, a connection electrode on the insulating layer and connecting a first contact region and a second contact region of adjacent light emitting cells, a transparent support substrate on the first surface of the plurality of light emitting cells, and a transparent bonding layer between the plurality of light emitting cells and the transparent support substrate.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pun Jae Choi, Jacob Chang-Lin Tarn, Han Kyu Seong, Jin Hyuk Song, Yoon Joon Choi
  • Patent number: 10366915
    Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10366990
    Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10366926
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10367079
    Abstract: A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity. The semiconductor device further includes a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Jr-Jung Lin, Shih-Hao Chen, Chih-Han Lin, Mu-Tsang Lin, Yung Jung Chang
  • Patent number: 10365561
    Abstract: Shrinkage and mass losses are reduced in photoresist exposure and post exposure baking by utilizing a small group which will decompose. Alternatively a bulky group which will not decompose or a combination of the small group which will decompose along with the bulky group which will not decompose can be utilized. Additionally, polar functional groups may be utilized in order to reduce the diffusion of reactants through the photoresist.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Han Lai, Ching-Yu Chang, Chen-Hau Wu
  • Patent number: 10366966
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Publication number: 20190223776
    Abstract: A urinary bladder irrigation device includes: a first pipe, a second pipe, a third pipe, a liquid supply member, a liquid collection member, a detection member, and an elevation member. The first pipe has a first opening at one end thereof. The second pipe has a second opening at one end thereof. The third pipe has an end connected to another end of the first pipe and another end of the second pipe and has a third opening at another end thereof. The liquid supply member is connected to the first opening. The liquid collection member is connected to the second opening. The detection member is positioned in the second pipe. The elevation member accommodates the detection member.
    Type: Application
    Filed: January 24, 2019
    Publication date: July 25, 2019
    Inventors: Chen-Hsun Weng, Ming-Chien Hung, Wen-Horng Yang, Chien-Hui Ou, Ming-Huang Chen, Chih-Han Chang
  • Publication number: 20190229215
    Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng