Patents by Inventor Han Chou

Han Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250234617
    Abstract: Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. The structure includes a source/drain region disposed over a substrate, an interlayer dielectric layer disposed over the source/drain region, a first conductive feature disposed over the source/drain region, a gate electrode layer disposed over the substrate, and a dielectric layer surrounding the first conductive feature. The dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature and a second portion disposed between the first conductive feature and the gate electrode layer, at least a portion of the first portion has a first thickness, and the second portion has a second thickness substantially greater than the first thickness.
    Type: Application
    Filed: May 13, 2024
    Publication date: July 17, 2025
    Inventors: Meng-Han CHOU, Wei-Ting CHANG, Su-Hao LIU, Chi On CHUI, Chien-Hao CHEN
  • Patent number: 12346420
    Abstract: A method for protecting application programs of electronic computing devices, which includes arranging a fingerprint detection device at least partially overlapped on the display screen of the electronic computing device, setting a verification area on the display screen to lock or unlock the software applications or files framed by the verification area and to protect the framed software applications or files from unauthorized retrieving.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: July 1, 2025
    Assignee: Decentralized Biotechnology Intelligence Co., Ltd.
    Inventors: Yen-Han Chou, Yao-Sheng Chou
  • Publication number: 20250211474
    Abstract: A method includes receiving, at a user equipment device (UE) from a transmission and reception point (TRP), an uplink CSI measurement configuration including a sounding reference signal (SRS) resource configuration indicating one or more of SRS resource randomization configurations of a cyclic shift, a comb offset, and a time domain orthogonal cover code (TD-OCC); and transmitting SRSs in a sequence of symbols, according to the SRS resource configuration, wherein the SRSs are determined according to the one or more of SRS resource randomization configurations of the cyclic shift, the comb offset, and the TD-OCC, values of the one or more of SRS resource randomization configurations being randomized symbol-by-symbol according to at least one of a cell-specific identity (IDcell) and a UE-specific identity (IDue).
    Type: Application
    Filed: April 13, 2023
    Publication date: June 26, 2025
    Inventors: Tzu-Han CHOU, Chia-Hao YU, Yahia Ahmed Mahmoud Mahmoud SHABARA, Parisa CHERAGHI
  • Publication number: 20250210414
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.
    Type: Application
    Filed: March 12, 2025
    Publication date: June 26, 2025
    Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Meng-Han Chou, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12323779
    Abstract: A sound source localization system includes a microphone array composed of a plurality of microphones each converting sound wave into a corresponding voice signal; a room shape estimator that determines a room shape including a location map and a corresponding template voice feature map composed of template voice features associated with a virtual sound source disposed at different locations respectively, and outputs a room reliability indicating confidence about the determined room shape; a lookup table (LUT) that pre-stores the location map and the corresponding template voice feature map; and a localizer that determines a location of a sound source according to the room reliability and similarity between a voice feature associated with the sound source and the template voice features of the template voice feature map.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: June 3, 2025
    Assignee: Himax Technologies Limited
    Inventors: Ti-Wen Tang, Tzu-Hsu Chen, Chin-Kuei Hsu, Ching-Han Chou
  • Publication number: 20250158678
    Abstract: Various solutions for channel information feedback with respect to user equipment and network apparatus in mobile communications are described. An apparatus may receive a reference signal transmitted by a network side including one or more than one network nodes. The apparatus may derive a channel response information observed by a receiving domain of the apparatus according to the reference signal. The apparatus may decompose the channel response information into a two-dimensional domain to obtain a linear combination coefficient representation of the channel response information in the two-dimensional domain. The apparatus may report a compressed channel information to the network side based on the linear combination coefficient representation and the two-dimensional domain.
    Type: Application
    Filed: March 20, 2023
    Publication date: May 15, 2025
    Inventors: Chia-Hao YU, Tzu-Han CHOU, Chin-Kuo JAO, Jiann-Ching GUEY
  • Publication number: 20250143664
    Abstract: A wearable heart sound detection device includes an acoustic sensing device for collecting heart sound signals of user's body. A wireless transmission device is connected to transmit and receive data, an e-SIM embedded in the wearable heart sound detection device, wherein said acoustic sensing device includes a capacitive sound sensor, a piezoelectric sound sensor or the combination thereof. A circuit assembly electrically is connected with the capacitive sound sensor or said piezoelectric sound sensor, wherein the capacitive sound sensor and the piezoelectric sound sensor are integrated on a flexible substrate. The e-SIM is compatible with a wireless transmission protocol selected from a group of WiFi, 4G, 5G, 6G or any combination thereof.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Inventors: Yao-Sheng CHOU, Wei-Sheng Su, Hsiao-Yi Lin, Lin-Yi Jiang, Yen-Han Chou
  • Publication number: 20250133771
    Abstract: A method of forming a semiconductor device includes the following operations. A substrate is provided with a recess therein. An insulating layer is formed on a bottom of the recess. A seed layer is formed on the insulating layer. An epitaxial layer is grown in the recess from the seed layer.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Syuan SIAO, Yu Tao Sun, Meng-Han Chou, Su-Hao Liu, Chi On Chui
  • Publication number: 20250120967
    Abstract: The present disclosure generally relates to novel multiple target inhibitor of tyrosine kinases (TKs) which can suppress angiogenesis, metastasis, oncogenesis, and/or immune regulation activities by inhibiting TKs and have very potent immunomodulatory activity. The present disclosure also relates to a method of using the tyrosine kinase inhibitors, alone or in combination with HDAC inhibitor, for the treatment of cancers, in particular in cancer immunotherapy, by regulating the tumor microenvironment, including reducing tumor hypoxia, reducing lactic acid accumulation, activating CTL, inhibiting the number and activity of immunosuppressive cells, finally obtaining superior anti-cancer benefits and/or producing lasting immune memory.
    Type: Application
    Filed: October 15, 2024
    Publication date: April 17, 2025
    Inventors: Jia-Shiong CHEN, Mu-Hsuan YANG, Cheng-Han CHOU, Yi-Hong WU, Sz-Hao CHU, Ye-Su CHAO, Chia-Nan CHEN
  • Patent number: 12278141
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Meng-Han Chou, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20250098206
    Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.
    Type: Application
    Filed: December 4, 2024
    Publication date: March 20, 2025
    Inventors: Meng-Han Chou, Yi-Syuan Siao, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20250098187
    Abstract: A memory cell structure includes a transistor structure and a capacitor structure, where the capacitor structure includes a hydrogen absorption layer. The hydrogen absorption layer absorbs hydrogen, which prevents or reduces the likelihood of the hydrogen diffusing into an underlying metal-oxide channel of the transistor structure. In this way, the hydrogen absorption layer minimizes and/or reduces the likelihood of hydrogen contamination in the metal-oxide channel, which may enable a low current leakage to be achieved for the memory cell structure and reduces the likelihood of data corruption and/or failure of the memory cell structure, among other examples.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 20, 2025
    Inventors: Yu-Chien CHIU, Chen-Han CHOU, Ya-Yun CHENG, Ya-Chun CHANG, Wen-Ling LU, Yu-Kai CHANG, Pei-Chun LIAO, Chung-Wei WU
  • Publication number: 20250096041
    Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 20, 2025
    Inventors: Meng-Han Chou, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20250071742
    Abstract: Various solutions for channel information feedback with prior information with respect to user equipment and network apparatus in mobile communications are described. An apparatus may receive a reference signal transmitted by a network side including at least one network node. The apparatus may obtain at least one selected basis. The apparatus may derive a channel response information observed by a receiving domain of the apparatus according to the reference signal. The apparatus may decompose the channel response information into a preferred domain. The apparatus may determine a simplified linear combination coefficient representation of the channel response information in the preferred domain according to the selected basis. The apparatus May report a compressed channel information to the network side based on the simplified linear combination coefficient representation and the preferred domain.
    Type: Application
    Filed: March 21, 2023
    Publication date: February 27, 2025
    Inventors: Chia-Hao YU, Tzu-Han CHOU, Chin-Kuo JAO, Jiann-Ching GUEY
  • Patent number: 12217498
    Abstract: A defect inspection system is disclosed, and comprises a linear light source, N number of cameras, a display device, a tag reader, and a modular electronic device, in which the linear light source, the cameras and the modular electronic device are used for conducting a defect inspection of an article. On the other hand, the display device, the tag reader and the modular electronic device are adopted for conducting in production of at least one labeled example. Therefore, the modular electronic device is allowed to apply a machine learning process to an image classifier under using a training dataset containing the labeled examples, thereby producing at least one new defect recognition model or updating the existing defect recognition model.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: February 4, 2025
    Assignees: Kapito Inc.
    Inventors: Feng-Tso Sun, Yi-Ting Yeh, Feng-Yu Sun, Jyun-Tang Huang, Po-Han Chou
  • Patent number: 12213971
    Abstract: The present disclosure generally relates to compounds class I HDAC inhibitors, their production and applications. The compounds possess epigenetic immunomodulatory activities in the tumor microenvironment (TME) and thus inhibit growth of tumor cells.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: February 4, 2025
    Assignee: GREAT NOVEL THERAPEUTICS BIOTECH & MEDICALS CORPORATION
    Inventors: Jia-Shiong Chen, Mu-Hsuan Yang, Yi-Hong Wu, Sz-Hao Chu, Cheng-Han Chou, Ye-Su Chao, Chia-Nan Chen
  • Patent number: 12211789
    Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: January 28, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming Hu, Shu-Jui Chang, Chen-Han Chou, Yen-Teng Ho, Chia-Hsing Wu, Kai-Yu Peng, Cheng-Hung Shen
  • Patent number: 12199156
    Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Chou, Yi-Syuan Siao, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12191651
    Abstract: An overcurrent protection circuit, a memory storage device, and an overcurrent protection method are disclosed. The overcurrent protection circuit includes a load switch, a first mirror circuit, a second mirror circuit, and a control circuit. The first mirror circuit is configured to generate a first node voltage in a state that a voltage difference between two terminals of the load switch is within a first voltage region. The second mirror circuit is configured to generate a second node voltage in a state that the voltage difference between the two terminals of the load switch is within a second voltage region. The control circuit is configured to cut off the load switch according to at least one of the first node voltage and the second node voltage to perform an overcurrent protection. The first voltage region is different from the second voltage region.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: January 7, 2025
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Shu-Han Chou
  • Patent number: 12183632
    Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Chou, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo