Patents by Inventor Han Chou

Han Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220321312
    Abstract: A partial sounding method for sounding-reference-signal (SRS) is proposed. The network node may transmit higher-layer signal configuring a fractional SRS resource for partial sounding in configured resource blocks (RBs) to user equipment (UE). The UE may determine an SRS sequence length and a frequency-domain starting position of the fractional SRS resource based on the higher-layer signal to increase the SRS capacity.
    Type: Application
    Filed: March 4, 2022
    Publication date: October 6, 2022
    Inventors: Tzu-Han Chou, Cheng-Rung Tsai, Jiann-Ching Guey
  • Publication number: 20220319982
    Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.
    Type: Application
    Filed: August 23, 2021
    Publication date: October 6, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
  • Patent number: 11456383
    Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
  • Publication number: 20220300590
    Abstract: A method for protecting application programs of electronic computing devices, which includes arranging a fingerprint detection device at least partially overlapped on the display screen of the electronic computing device, setting a verification area on the display screen to lock or unlock the software applications or files framed by the verification area and to protect the framed software applications or files from unauthorized retrieving.
    Type: Application
    Filed: November 1, 2021
    Publication date: September 22, 2022
    Inventors: Yen-Han Chou, Yao-Sheng Chou
  • Publication number: 20220301364
    Abstract: The present invention provides a driver and passenger behavior information system which includes a sensing device to detect a driving behavior signal, wherein the sensing device is set at the vehicle control associated apparatus for controlling the vehicle and sensing the driving behavior signal by the sensing device, a driving behavior record device is coupled to the sensing device to store the sensing signals.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 22, 2022
    Inventors: Yen-Han CHOU, Yao-Sheng CHOU
  • Publication number: 20220300965
    Abstract: A smart transaction device with multiple fingerprint recognition includes a device body having a first surface and a second surface on the opposite side, a plurality of fingerprint sensing devices being respectively arranged on the first surface and the second surface to individually sense the fingerprints of different fingers of a user and store them in the memory as comparison data.
    Type: Application
    Filed: November 1, 2021
    Publication date: September 22, 2022
    Inventors: Yen-Han Chou, Yao-Sheng Chou
  • Publication number: 20220251218
    Abstract: The invention relates to a method of overcoming immune suppression in tumor microenvironment or stimulating immune response against cancer, comprising administering to a subject a combination of a histone deacetylase (HDAC) inhibitor and a tyrosine kinase inhibitor (TKI).
    Type: Application
    Filed: February 10, 2021
    Publication date: August 11, 2022
    Inventors: Cheng-Han CHOU, Yi-Hong WU, Jia-Shiong CHEN, Ye-Su CHAO, Chia-Nan CHEN
  • Publication number: 20220230911
    Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Inventors: Kuo-Ju Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Meng-Han Chou
  • Publication number: 20220216147
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.
    Type: Application
    Filed: March 23, 2022
    Publication date: July 7, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
  • Patent number: 11382020
    Abstract: Aspects of the disclosure provide an electronic device including processing circuitry and a method for beam failure recovery. The processing circuitry can determine whether beam failure occurs on at least one of a plurality of cells configured for serving an electronic device. When the beam failure is determined to occur on the at least one of the plurality of cells, the processing circuitry can send an uplink message that includes a first portion and a second portion to a network. The first portion indicating the beam failure is transmitted using a physical random access channel (PRACH) resource. The second portion indicates at least one of cell information of the at least one of the plurality of cells and new beam information of one or more new candidate beams for the at least one of the plurality of cells and is transmitted using a physical uplink shared channel (PUSCH) resource.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: July 5, 2022
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Gyu Bum Kyung, Weidong Yang, Tzu-Han Chou
  • Patent number: 11363516
    Abstract: Aspects of the disclosure provide an electronic device including processing circuitry and a method for beam failure recovery (BFR). When beam failure is determined to occur on at least one of a plurality of cells configured for the electronic device, the processing circuitry can send a BFR scheduling request (SR) to a network. The BFR SR can indicate the beam failure and requesting resources to report the beam failure. The processing circuitry can receive priority scheduling for the resources from the network. The processing circuitry can send a BFR request (BFRQ) using the resources. The BFRQ can indicate cell information of the at least one of the plurality of cells and new beam information of one or more new candidate beams for the at least one of the plurality of cells.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: June 14, 2022
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Gyu Bum Kyung, Tzu-Han Chou, Weidong Yang
  • Patent number: 11329435
    Abstract: An AC power input socket includes a casing and at least two conductive pins. The casing comprises a connection side and an output side based on performance of the AC power input socket. The casing is provided with an accommodating groove at the connection side, each of the two conductive pins includes a power connection section located in the accommodating groove, an output section extending from the power connection section and passing through the casing to be exposed on the output side, and a capacitor connecting section extending from an end of the output section. Each of the conductive pins is provided with a through hole in the output section for disposing an electric wire, and the capacitor connecting section provides a capacitor pin to be connected thereon, so that the capacitor pin and the electric wire do not need to be disposed at a same hole position.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: May 10, 2022
    Assignee: INNOTRANS TECHNOLOGY CO., LTD.
    Inventor: Tsung-Han Chou
  • Patent number: 11289417
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
  • Publication number: 20220059405
    Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.
    Type: Application
    Filed: August 24, 2020
    Publication date: February 24, 2022
    Inventors: Meng-Han Chou, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220060233
    Abstract: Examples pertaining to reference signal sharing in mobile communications are described. An apparatus (e.g., UE) receives a plurality of reference signals comprising a first set of reference signals and a second set of reference signals. The apparatus performs time or frequency tracking based on the plurality of reference signals. Alternatively, the apparatus generates a channel state information (CSI) report associated with the plurality of reference signals and transmits the CSI report to a network.
    Type: Application
    Filed: August 2, 2021
    Publication date: February 24, 2022
    Inventors: Lung-Sheng Tsai, Jiann-Ching Guey, Tzu-Han Chou
  • Patent number: 11218288
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives an indication for transmitting a particular DMRS sequence in an uplink transmission. The particular DMRS sequence is time domain based. The UE generates the particular DMRS sequence. The UE modulates the particular DMRS sequence to obtain a set of symbols. The UE maps a plurality of symbols of the set of symbols to a plurality of subcarriers. The UE transmits the plurality of symbols on the plurality of subcarriers.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: January 4, 2022
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Han Chou, Weidong Yang, Chao-Cheng Su, Jiann-Ching Guey
  • Publication number: 20210407808
    Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.
    Type: Application
    Filed: April 15, 2021
    Publication date: December 30, 2021
    Inventors: Meng-Han Chou, Kuan-Yu Yeh, Wei-Yip Loh, Hung-Hsu Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20210379032
    Abstract: The present disclosure generally relates to compounds class I HDAC inhibitors, their production and applications. The compounds possess epigenetic immunomodulatory activities in the tumor microenvironment (TME) and thus inhibit growth of tumor cells.
    Type: Application
    Filed: April 28, 2021
    Publication date: December 9, 2021
    Inventors: Jia-Shiong CHEN, Mu-Hsuan YANG, Yi-Hong WU, Sz-Hao CHU, Cheng-Han CHOU, Ye-Su CHAO, Chia-Nan CHEN
  • Patent number: 11188516
    Abstract: An approach for consistent database recovery for distributed database systems uses “synchronization points”. A synchronization point is a global timestamp for which across all nodes of a distributed database system, the nodes have stored change records for any transaction occurring at and before the synchronization point in persistent logs. Each node may employ asynchronous flushing. However, on a periodic basis, each node coordinates to establish a synchronization point, which may entail ensuring change records for transactions that committed at or before the synchronization point are stored in persistent logs. In effect, a synchronization point represents that any transaction committed at or before the synchronization point has been durably committed.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: November 30, 2021
    Assignee: Oracle International Corproation
    Inventors: Derek Taylor, Chi-Kim Hoang, Yu-Han Chou, Varadarajan Aravamudhan
  • Publication number: 20210358675
    Abstract: A pin structure of a transformer bobbin is provided. The transformer bobbin includes a winding part on which at least one winding is wound, and at least one wire outlet part arranged on a side of the winding part. The pin structure includes at least two accommodating slots arranged at the wire outlet part, and at least two conductive pins. Each of the accommodating slots has two first sections and a second section connected to the two first sections. Each of the conductive pins corresponds to one of the accommodating slots, and includes a connection section in the second section and two exposed sections connected to the connection section and extending to an outside of the winding part via the two first sections. One exposed section can perform socket welding, and the other one is bendable to define the end of the winding with the wire outlet part.
    Type: Application
    Filed: May 10, 2021
    Publication date: November 18, 2021
    Inventor: Tsung-Han CHOU