Patents by Inventor Han Fang
Han Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190088756Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack disposed over the substrate and overlapping the first fin structure. The first gate stack includes a first work function layer, a first gate electrode, and a first hard mask layer, the first gate electrode is over the first work function layer, the first hard mask layer is over the first gate electrode, the first gate electrode has a first convex top surface protruding beyond a first top surface of the first work function layer. The semiconductor device structure includes a second gate stack disposed over the substrate and overlapping the second fin structure.Type: ApplicationFiled: November 8, 2018Publication date: March 21, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Han FANG, Chang-Yin CHEN, Ming-Chia TAI, Po-Chi WU
-
Patent number: 10134861Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack overlapping the first fin structure. The first gate stack has a first width. The first gate stack includes a first work function layer. A first top surface of the first work function layer is positioned above the first fin structure by a first distance. The semiconductor device structure includes a second gate stack disposed overlapping the second fin structure. The first width is less than a second width of the second gate stack. A second top surface of a second work function layer of the second gate stack is positioned above the second fin structure by a second distance. The first distance is less than the second distance.Type: GrantFiled: October 8, 2014Date of Patent: November 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Han Fang, Chang-Yin Chen, Ming-Chia Tai, Po-Chi Wu
-
Patent number: 9948320Abstract: Methods and systems are provided for the compression and decompression of data. The compression and decompression of data may include partitioning the data into chunks, analyzing the individual chunks to determine the best compression and decompression encoders to utilize for the next data chunk of a data file. In compressing and decompressing using the mentioned technique, the data is delivered to the requesting client in an efficient and speedy manner.Type: GrantFiled: September 15, 2017Date of Patent: April 17, 2018Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Yuqing Yang, Han Fang, Shaohua Yang
-
Publication number: 20180047633Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.Type: ApplicationFiled: October 23, 2017Publication date: February 15, 2018Inventors: Chai-Wei Chang, Po-Chi Wu, Wen-Han Fang
-
Patent number: 9864549Abstract: Systems and methods relating generally to data storage, and more particularly to systems and methods for encoding to modify the size of an information set.Type: GrantFiled: February 29, 2016Date of Patent: January 9, 2018Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Shaohua Yang, Han Fang, Wu Chang, Kelly Fitzpatrick
-
Patent number: 9799565Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.Type: GrantFiled: February 18, 2015Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chai-Wei Chang, Po-Chi Wu, Wen-Han Fang
-
Publication number: 20170249105Abstract: Systems and methods relating generally to data storage, and more particularly to systems and methods for encoding to modify the size of an information set.Type: ApplicationFiled: February 29, 2016Publication date: August 31, 2017Inventors: Shaohua Yang, Han Fang, Wu Chang, Kelly Fitzpatrick
-
Publication number: 20170062617Abstract: A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conductive diffusion barrier layer and extending into the opening, and performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer. After the dry etch, a conductive layer is formed over the conductive diffusion barrier layer and extending into the opening.Type: ApplicationFiled: November 9, 2016Publication date: March 2, 2017Inventors: Wen-Han Fang, Po-Chi Wu
-
Patent number: 9570105Abstract: Systems and methods are disclosed for data processing, and more particularly for equalizing a data signal during both real time (i.e., on the fly) and retry operation. The system may include a first equalizer circuit operable to equalize a first sample set, and a second equalizer circuit operable to equalize a second sample set. The system may include a third equalizer circuit operable to equalize a summed data set to yield a third equalized output. The system may include a summation circuit connected to the first equalizer circuit, the second equalizer circuit, and a switch circuit. The summation circuit is operable to sum at least the first equalized data set and the second equalized data set to yield the summed data set. The switch circuit selectively provides the third equalized data set to the summation circuit.Type: GrantFiled: December 14, 2015Date of Patent: February 14, 2017Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: George Mathew, Jongseung Park, Han Fang, Richard Rauschmayer
-
Patent number: 9496402Abstract: A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conductive diffusion barrier layer and extending into the opening, and performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer. After the dry etch, a conductive layer is formed over the conductive diffusion barrier layer and extending into the opening.Type: GrantFiled: July 16, 2015Date of Patent: November 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Han Fang, Po-Chi Wu
-
Patent number: 9443133Abstract: A method for completing message-playback on an electronic device involves: detection of an unplayed message storage, determining the facial images of the message recipients associated with the unplayed message, capturing facial images of members in front of the electronic device, comparing the facial images associated with the unplayed message with the captured facial image, determining whether there is at least one member who has not received this message who is in front of the electronic device according to the comparison, and if so playing the message.Type: GrantFiled: March 28, 2014Date of Patent: September 13, 2016Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Mei-Ju Chen, Han-Fang Tu, Kuan-Jung Chiu
-
Patent number: 9437472Abstract: Some embodiments of the present disclosure provide a semiconductor structure with a reduced line feature. The semiconductor structure includes a substrate, a first active region in the substrate and having a first sidewall, a second active region in the substrate and having a second sidewall, an isolation region contacting the first sidewall and the second sidewall. The above-mentioned semiconductor structure possesses a width of a top surface of the isolation region less than 50 nm and a width of a bottom surface of the isolation region more than 20 nm. Some embodiments provide a method for controlling a semiconductor line feature in a wafer, including patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer, forming a trench on the wafer correlated to the line feature by performing a plasma dry etch over the wafer, and filling the trench with isolation materials.Type: GrantFiled: February 27, 2014Date of Patent: September 6, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Han Fang, Po-Chi Wu
-
Publication number: 20160190013Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.Type: ApplicationFiled: February 18, 2015Publication date: June 30, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chai-Wei CHANG, Po-Chi WU, Wen-Han FANG
-
Publication number: 20160111543Abstract: A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conductive diffusion barrier layer and extending into the opening, and performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer. After the dry etch, a conductive layer is formed over the conductive diffusion barrier layer and extending into the opening.Type: ApplicationFiled: July 16, 2015Publication date: April 21, 2016Inventors: Wen-Han Fang, Po-Chi Wu
-
Publication number: 20160104704Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack overlapping the first fin structure. The first gate stack has a first width. The first gate stack includes a first work function layer. A first top surface of the first work function layer is positioned above the first fin structure by a first distance. The semiconductor device structure includes a second gate stack disposed overlapping the second fin structure. The first width is less than a second width of the second gate stack. A second top surface of a second work function layer of the second gate stack is positioned above the second fin structure by a second distance. The first distance is less than the second distance.Type: ApplicationFiled: October 8, 2014Publication date: April 14, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Wen-Han FANG, Chang-Yin CHEN, Ming-Chia TAI, Po-Chi WU
-
Patent number: 9304910Abstract: A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.Type: GrantFiled: January 13, 2014Date of Patent: April 5, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Qi Zuo, Kuhong Jeong, Shu Li, Xiang Wang, Han Fang, Shaohua Yang
-
Patent number: 9185527Abstract: A server includes a communication module, a database and a processor. The communication module receives identification information of a user of a mobile terminal and a movement status and a geographic position of the user from the mobile terminal. The processor determines real time traffic condition of the geographic position of the user according to the real time traffic information of the area where the user is located stored in the database and evaluates a time period to be spent from the geographic position of the user to the display terminal according to the movement status of the user and the real time traffic condition of the area. The communication module further transmits the geographic position of the user, the evaluated time period and the identification information of the user to the display terminal. A system including the server and a method of displaying a user status are also disclosed.Type: GrantFiled: October 22, 2013Date of Patent: November 10, 2015Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Kuan-Jung Chiu, Han-Fang Tu, Mei-Ju Chen
-
Publication number: 20150243547Abstract: Some embodiments of the present disclosure provide a semiconductor structure with a reduced line feature. The semiconductor structure includes a substrate, a first active region in the substrate and having a first sidewall, a second active region in the substrate and having a second sidewall, an isolation region contacting the first sidewall and the second sidewall. The above-mentioned semiconductor structure possesses a width of a top surface of the isolation region less than 50 nm and a width of a bottom surface of the isolation region more than 20 nm. Some embodiments provide a method for controlling a semiconductor line feature in a wafer, including patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer, forming a trench on the wafer correlated to the line feature by performing a plasma dry etch over the wafer, and filling the trench with isolation materials.Type: ApplicationFiled: February 27, 2014Publication date: August 27, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: WEN-HAN FANG, PO-CHI WU
-
Publication number: 20150161045Abstract: A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.Type: ApplicationFiled: January 13, 2014Publication date: June 11, 2015Applicant: LSI CorporationInventors: Qi Zuo, Kuhong Jeong, Shu Li, Xiang Wang, Han Fang, Shaohua Yang
-
Patent number: D788970Type: GrantFiled: December 29, 2015Date of Patent: June 6, 2017Inventor: Han-Fang Tu